PIC16(L)F18326/18346
Full-Featured, 14/20 Low Pin Count Microcontrollers with XLP
Description
PIC16(L)F18326/18346 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.
The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
• C Compiler Optimized RISC Architecture
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• Up to Three 16-bit Timers
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRTE)
• Brown-out Reset (BOR) Option
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
Memory
• 28 Kbytes Program Flash Memory
• 2 KB Data SRAM Memory
• 256B of EEPROM
• Direct, Indirect and Relative Addressing Modes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18326/18346)
- 2.3V to 5.5V (PIC16F18326/18346)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 40 nA @ 1.8V, typical
• Watchdog Timer: 250 nA @ 1.8V, typical
• Secondary Oscillator: 300 nA @ 32 kHz
• Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 37 A/MHz @ 1.8V, typical
Power-Saving Functionality
• IDLE mode: ability to put the CPU core to Sleep
while internal peripherals continue operating from
the system clock
• DOZE mode: ability to run the CPU core slower
than the system clock used by the internal
peripherals
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD): peripheral
power disable hardware module to minimize
power consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
- Four CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Two CWGs
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Capture/Compare/PWM (CCP) modules:
- Four CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Pulse-Width Modulators (PWM):
- Two 10-bit PWMs
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
-
-
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• Serial Communications:
- EUSART
- RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
- Master Synchronous Serial Port (MSSP)
- SPI
- I2C, SMBus, PMBus™ compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 1
