an integrated voltage reference (VBB) is provided. Single-ended CLK input operation is limited to VCC ≥ 3.0V in PECL mo.

The SY10/100EP16U is a 2.5/3.3V, high-speed, fully differential ECL Receiver/Driver that can process clock signals as fast as 3GHz or data patterns up to 2.5Gbps. The differential input includes an internal 75kΩ pulldown resistor on both the true and.

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