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Micrel Semiconductor

PL500-15 Datasheet Preview

PL500-15 Datasheet

Low Phase Noise VCXO

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FE AT UR E S
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
PIN CONFIGURATION
VCXO with Divider Selection (DIVSEL) input pin
PL500-15: ÷8, ÷16
PL500-16: ÷2, ÷4
VCXO output for the 1MHz to 18MHz range
16MHz to 36MHz fundamental crystal input.
Low phase noise (-130 dBc @ 10kHz offset
using a 35.328MHz crystal).
LVCMOS output with OE tri-state control.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
± 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or DIE.
DESCRIPTION
The PL500-15/16 is a low cost, high performance
and low phase noise VCXO for the 1MHz to 18MHz
range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter
(2.5 ps RMS period jitter) makes this chip ideal for
applications requiring voltage controlled frequency
sources. Input crystal can range from 16MHz to
36MHz (fundamental resonant mode).
BLOCK DIAGRAM
XIN
VCON
DIVSEL^
GND
18
27
36
45
SOP-8L
XOUT
OE^
VDD
CLK
VCON
GND
XIN
1
2
3
6 CLK
5 VDD
4 XOUT
SOT23-6L*
^: Denotes internal Pull-up
*: SOT package offers single divider option only
DIVIDER SELECTION LOGIC LEVELS
Part #
DivSel State
Operation
PL500-15
1 (Default)*
0
PL500-16
1 (Default)*
0
* Setting for SOT23 package
÷16
÷8
÷4
÷2
DIVSEL
XIN
XOUT
VCON
Xtal
Osc
Varicap
Selectable
Divider
CLK
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 7/01/10 Page 1




Micrel Semiconductor

PL500-15 Datasheet Preview

PL500-15 Datasheet

Low Phase Noise VCXO

No Preview Available !

DIE PAD LAYOUT
32 mil
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
(812,986)
DIE SPECIFICATIONS
1 XIN
8
XOUT
OE^ 7
2 VCON
VDD 6
3 DIVSEL^
CLK 5
4 GND
DIE ID: PL500-15: C500A-1111-12
PL500-16: C500A-1111-11
Y (0,0)
X Note: ^ denotes internal pull up
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
8 mil
DIE PAD ASSIGNMENT
Name
Pin#
SOP-8 SOT23-6
XIN 1
3
VCON
2
1
DIVSEL
3
-
GND 4
CLK 5
VDD 6
2
6
5
OE 7
-
XOUT
8
4
Die Pad Position
X (m) Y (m)
94.183 768.599
94.157 605.029
94.183 331.756
94.193
715.472
715.307
140.379
203.866
455.726
715.472 626.716
476.906 888.881
Type
I
P
I
P
O
P
I
I
Description
Crystal input pin.
Frequency Control Voltage input pin.
Divider Selection input pin. Default Logic 1 for
SOT23 package. See Divider Selection Logic
Levels table on Page 1.
Ground pin.
Output clock pin.
VDD power supply pin.
Output Enable input pin. Disables the output
when low. Internal pull-up enables output by
default if pin is not connected to low. Default
“Enabled” (Logic 1) for SOT23 package.
Crystal output pin.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 7/01/10 Page 2


Part Number PL500-15
Description Low Phase Noise VCXO
Maker Micrel Semiconductor
Total Page 5 Pages
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