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Micrel

PL685-28 Datasheet Preview

PL685-28 Datasheet

19MHz to 250MHz Low Phase-Noise XO

No Preview Available !

(Preliminary) PL685-28
FE AT UR E S
19MHz to 250MHz Low Phase-Noise XO
PAD CONFIGURATION
< 0.6ps RMS phase jitter (12kHz to 20MHz) at
155.52MHz
30ps max peak to peak period jitter
8bit Switch Capacitor for ±50PPM crystal CLoad
tuning
о Load Capacitance Tuning Range: 8pF to 12pF
Ultra Low-Power Consumption
о < 90 mA @155MHz PECL output
о <10A at Power Down (PDB) Mode
Input Frequency:
о Fundamental Crystal: 19MHz to 40MHz
Output Frequency:
о 19MHz to 250MHz output.
Output types: LVPECL.
Programmable OE input polarity selection.
Power Supply: 3.3V, ±10%
Operating Temperature Ranges:
о Commercial: 0C to 70C
о Industrial: -40C to 85C
Available in Die or Wafer
DESCRIPTION
The PL685-28 is a Dual LC core monolithic IC clock,
capable of maintaining sub-1ps RMS phase jitter,
while covering a wide frequency output range up to
250MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 40 MHz. The PL685-28 is
designed to address the demanding requirements of
high performance applications such as Fiber
Channel, serial ATA, Ethernet, SAN, SONET/SDH,
etc.
65 mil
SCLK 9
8
Die ID
OE/PDB/
SDIO
DNC
10
11
GND_ANA
GND_DIG
GND_BUF
12
13
14
(0,0)
PL685
(1650,2250)
7
6 VDD_ANA
5 VDD_DIG
4 VDD_BUF
3 QB
2 VDD_BUF
1Q
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 88.6 mil
GND
80 micron x 80 micron
8 mils
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
OE
State
0
0 (Default)
1
Output enabled
Tri-state
1 (Default)
0
1 (Default)
Tri-state
Output enabled
BLOCK DIAGRAM
OE/PDB
XIN/REF
XOUT
Xtal
Osc
(Default pre-programmed output path)
PD/CP
LF HF
LCVCOs
Pre-scalar
4/6
/2
Programmable Function
M Divider
(5 bit)
P Divider
(4 bit)
/2
Q
QB
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 1




Micrel

PL685-28 Datasheet Preview

PL685-28 Datasheet

19MHz to 250MHz Low Phase-Noise XO

No Preview Available !

(Preliminary) PL685-28
19MHz to 250MHz Low Phase-Noise XO
PAD ASSIGNMENT
Name
Pad # X (m) Y (m)
Description
Q
VDD_BUF
QB
VDD_BUF
VDD_DIG
VDD_ANA
XOUT
XIN
SCLK
1
2
3
4
5
6
7
8
9
OE/PDB/SDIO 10
DNC
GND_ANA
GND_DIG
GND_BUF
11
12
13
14
1551 220 Output buffer
1551 448 VDD connection for buffer circuitry
1551 676 Output buffer
1551 1390 VDD connection for buffer circuitry
1551 1552 VDD connection for digital circuitry
1551 1790 VDD connection for analog circuitry
1503 2156 Output connection to crystal
630 2156 Crystal input connection
99
2060
The serial interface uses this pin for the serial clock input
(SCLK), during programming.
This pin may be programmed as output enable (OE), or power-
down (PDB) pin.
99 1256 The serial interface uses this pin for the serial data input (SDIO)
during programming. This pin incorporates an Internal pull -up
resistor of 60Kfor OE, PDB operations.
99 970 Do not connect
99 700 GND connection for analog circuitry
99 532 GND connection for digital circuitry
99 364 GND connection for buffer circuitry
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/02/11 Page 2


Part Number PL685-28
Description 19MHz to 250MHz Low Phase-Noise XO
Maker Micrel
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