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PL613-21 Datasheet Preview

PL613-21 Datasheet

Programmable 3-PLL Clock IC

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PL613-21
Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC
FE AT UR E S
Designed for PCB Space Savings with 3 Low-
Power Programmable PLLs
Ultra Low-Power Consumption
Ultra-Low Power Down Mode, <5A Typical
CLK1 Capable of Generating 32.768kHz
Individual Output Buffer VDD Pins for Flexible
Output Voltages, 1.8V to 3.3V, ±10%
Individual PLL Power Down Control
Output Frequency (based on VDD_CORE voltage):
o <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
Input Frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
Active Low or Hi-Z Disabled Output State
1.8V to 3.3V, ±10% Core Power Supply
1.8V to 3.3V, ±10% Buffer Power Supply
Operating Temperature Ranges:
o Commercial: 0C to 70C
o Industrial: -40C to 85C
Available in GREEN/RoHS Compliant 3x3 QFN
Package
PIN CONFIGURATION
PDB4
CLK4
VDD4
PDB1
12 11 10 9
13 8
14 P61321 7
XXX(I)
15
LLL
6
16 5
1 23 4
CLK3
PDB2_3
VDD2_3
CLK2
QFN-16L Package
DESCRIPTION
The PL613-21 is an advanced three PLL design based on PicoPLL, the world’s smallest programmable clock
technology. This advanced technology allows the PL613 -21 to fit in to a small 3x3mm QFN package for high
performance, low-power, small form-factor applications. By using the individual output buffer VDD pins, the
PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to generate kHz
outputs and is ideal for generating 32.768kHz outputs.
The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding
clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to
Low (4mA), Standard (8mA) or High (16mA) drive. In addition, the disabled state of the clock outputs can be
programmed as Hi-Z or Active Low.
Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613 -21 offers superior
phase noise, jitter and power consumption performance.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 8/11/10 Page 1




Micrel

PL613-21 Datasheet Preview

PL613-21 Datasheet

Programmable 3-PLL Clock IC

No Preview Available !

PL613-21
Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC
BLOCK DIAGRAM
XIN/FIN
XOUT
Xtal FREF
Osc
FREF
PLL1
VCO1
5-bit ÷
Odd/Even
÷
1,2,4,8
CLK2
VDD2_3*
CLK3
PDB2_3
PDB1
PDB4
FREF
PLL2
VCO2
15-bit ÷
Odd/Even
CLK1
VDD1*
PLL3
VCO3
5-bit ÷
Odd/Even
Programmable Function
* Separate buffer VDD’s allow output level control (1.8V ~ 3.3V, ±10%)
CLK4
VDD4*
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
QFN-16L
Type
Description
CLK1
1 O Programmable clock output
VDD1 2 P VDD connection for output buffer CLK1
GND
3, 4, 12
P GND connection
CLK2
5 O Programmable clock output
VD D2_ 3
PDB2_3*
6 P VDD connection for output buffers CLK2 and CLK3
7 I Power down input for PLL1, CLK2 and CLK3
CLK3
8 O Programmable clock output
VD D_ C O R E
XOUT
9 P VDD connection for core
10 O Crystal output pin. Do Not Connect when using FIN
XIN/FIN
11 I Crystal or Reference Clock input
PDB4*
13 I Power down input for PLL3 and CLK4
CLK4
14 O Programmable clock output
VDD4
PDB1*
15 P VDD connection for output buffer CLK4
16 I Power down input for PLL2 and CLK1
*Note: The PDB pins have no internal pull up or pull down resistors. These pins must be driven to a logic 1 (>1.62V) or logic 0 (<
0.4V) at startup to stabilize the corresponding output(s).
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 8/11/10 Page 2


Part Number PL613-21
Description Programmable 3-PLL Clock IC
Maker Micrel
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PL613-21 Datasheet PDF






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