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PL602-39 Datasheet Preview

PL602-39 Datasheet

750kHz - 800MHz Low Phase Noise Multiplier XO

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PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FE AT UR E S
PIN CONFIGURATION
Selectable 750kHz to 800MHz range.
Low phase noise output
-127dBc/Hz for 155.52MHz @ 10kHz offset
-115dBc/Hz for 622.08MHz @ 10kHz offset
LVCMOS (PL602-37), LVPECL (PL602-35 and
PL602-38) or LVDS (PL602-39) output.
12MHz to 25MHz crystal input.
No external crystal load capacitors required.
Output Enable selector.
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
1
6
2
1
5
3
1
4
4
1
3
5
1
2
6
1
1
7
1
0
89
TSSOP-16L
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
DESCRIPTION
The PL602-35 (LVPECL with inverted OE), PL602-37
(LVCMOS), PL602-38 (LVPECL), and PL602-39
(LVDS) are high performance and low phase noise XO
IC chips. They provide phase noise performance as
low as 127dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The very
low jitter makes them ideal for a wide range of applica-
tions, including SONET/SDH and FEC. They accept
fundamental parallel resonant mode crystals from
12MHz to 25MHz.
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14
PL602-3x
7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL[3:0]
XIN
XOUT
Oscillator
Amplifier
w/
integrated
load cap.
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
QFN-16L
^: Internal pull-up
*: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
Note: On QFN package there is a large center pad for thermal relief.
This pad needs to be connected to GND.
CLKT OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL602-3x
PL602-38
PL602-35
PL602-37
PL602-39
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by LVPECL levels for PL602-38
Logical states defined by LVCMOS levels for PL602-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 1




Micrel

PL602-39 Datasheet Preview

PL602-39 Datasheet

750kHz - 800MHz Low Phase Noise Multiplier XO

No Preview Available !

PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0011
0110
0111
1001
1010
1011
1100
1101
1110
1111
Note: SEL0 is not available (always “1”) for PL602-35 and PL602-38 in 3x3mm package
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
PIN DESCRIPTIONS PL602-35 and PL602-38 (see next page for PL602-37/-39)
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type
Description
XIN 2 12 I Crystal input (See Crystal Specification on page 4)
XOUT
3
13 I Crystal output (See Crystal Specification on page 4)
OE 6 16 I Output enable pin (See OE logic state table on page 1)
GND
7,8,9,10,14 1,2,3,4,8,11
P Ground connection
CLKT
11
5 O LVPECL True output
CLKC
13
7 O LVPECL Complementary output
SEL0
SEL1
SEL2
SEL3
16 Not available I
15 9 I Multiplier selector pins. These pins have an internal pull-
up that will default SEL to ‘1’ when not connected to
5 15 I GND.
4 14 I
VDD 1, 12 6,10 P +3.3V power supply.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 2


Part Number PL602-39
Description 750kHz - 800MHz Low Phase Noise Multiplier XO
Maker Micrel
Total Page 10 Pages
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