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PL585-28 Datasheet Preview

PL585-28 Datasheet

19MHz to 250MHz Low Phase-Noise VCXO

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(Preliminary) PL585-28
19MHz to 250MHz Low Phase-Noise VCXO
FE AT UR E S
< 0.6ps RMS phase jitter (12kHz to 20MHz)
at 155.52MHz
30ps max peak to peak period jitter
Ultra Low-Power Consumption
< 90mA @155MHz PECL output
<10A at Power Down (PDB) Mode
Input Frequency:
Fundamental Crystal: 19MHz to 40MHz
Output Frequency:
19MHz to 250MHz output.
Output type: LVPECL
High Linearity VCXO: <10% linearity
Pullability: ±150 ppm
Programmable OE input polarity selection.
Power Supply: 3.3V, ±10%
Operating Temperature Ranges:
Commercial: 0C to 70C
Industrial: -40C to 85C
Available in Die or Wafer
PIN CONFIGURATION
65 mil
VCON/
9
SCLK
8
Die ID
OE/PDB/
SDIO
DNC
10
11
GND_ANA
GND_DIG
GND_BUF
12
13
14
(0,0)
PL585
(1650,2250)
7
6 VDD_ANA
5 VDD_DIG
4 VDD_BUF
3 QB
2 VDD_BUF
1Q
DESCRIPTION
The PL585-28 is a Dual LC core monolithic IC clock,
capable of maintaining sub-picoseconds RMS phase
jitter, while covering a wide frequency output range
up to 250MHz, without the use of external
components. The high performance and high
frequency output is achieved using a low cost
fundamental crystal of between 19MHz and 40 MHz.
The PL585-28 is designed to address the demanding
requirements of high performance applications such
as Fiber Channel, serial ATA, Ethernet, SAN,
SONET/SDH, etc.
BLOCK DIAGRAM
OE/PDB
XIN/REF
XOUT
VCON
(Default pre-programmed output path)
Xtal
Osc
PD/CP
LF HF
LCVCOs
Varicap
Programmable Function
M Divider
(5 bit)
Pre-scalar
4/6
/2
P Divider
(4 bit)
/2
Q
QB
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/16/11 Page 1




Micrel

PL585-28 Datasheet Preview

PL585-28 Datasheet

19MHz to 250MHz Low Phase-Noise VCXO

No Preview Available !

DIE SPECIFICATIONS
1.65mm
8
9
Die ID
Y
10
X
11 0,0
12
13
14
(Preliminary) PL585-28
19MHz to 250MHz Low Phase-Noise VCXO
7 Chip size, active area 1.650mm x 2.250mm
Chip thickness
200µm ± 20µm
6
5
PAD size
80µm x 80µm
4
Scribe Line Dimension
X = 80µm
Y = 80µm
Chip Base
GND level
Die ID:
3
PL585-28DC
C685B C9-99-99-9
2
1
SCRIBE LINE
PAD ASSIGNMENT AND DESCRIPTION (The X/Y coordinates indicate pad centers)
Name
Pad # X (m) Y (m)
Description
Q
VDD_BUF
QB
VDD_BUF
VDD_DIG
VDD_ANA
XOUT
XIN
VCON/SCLK
1
2
3
4
5
6
7
8
9
OE/PDB/SDIO 10
DNC
GND_ANA
GND_DIG
GND_BUF
11
12
13
14
+726
+726
+726
+726
+726
+726
+678
-195
-726
-726
-726
-726
-726
-726
-905
-677
-449
+265
+427
+665
+1031
+1031
+935
+131
-155
-425
-593
-761
Output buffer
VDD connection for buffer circuitry
Output buffer
VDD connection for buffer circuitry
VDD connection for digital circuitry
VDD connection for analog circuitry
Output connection to crystal
Crystal input connection
Analog voltage pin for the VCXO. The serial interface uses this
pin for the serial clock input (SCLK), during programming.
This pin may be programmed as output enable (OE), or power-
down (PDB) pin.
The serial interface uses this pin for the serial data input (SDIO)
during programming. This pin incorporates an Internal pull -up
resistor of 60Kfor OE, PDB operations.
Do not connect
GND connection for analog circuitry
GND connection for digital circuitry
GND connection for buffer circuitry
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/16/11 Page 2


Part Number PL585-28
Description 19MHz to 250MHz Low Phase-Noise VCXO
Maker Micrel
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PL585-28 Datasheet PDF






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