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PL138-18 Datasheet Preview

PL138-18 Datasheet

2.5V-3.3V Low-Skew 1:10 Differential PECL Fanout Buffer

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PL138-18
2.5V-3.3V Low-Skew 1:10 Differential PECL Fanout Buffer
FEATURES
Ten differential 2.5V/3.3V LVPECL output pairs.
Output Frequency: ≤ 700 MHz.
Two selectable differential input pairs.
Translates any standard single-ended or differential
input format to LVPECL output. It can accept the
following standard input formats and more:
o LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML.
Output Skew: 25ps (typ.).
Part-to-part skew: 140ps (typ.).
Propagation delay: 1.5ns (typ.).
Additive Jitter: <100 fs (typ.).
Operating Supply Voltage: 2.375V ~ 3.63V.
Operating temperature range from -40°C to 85°C.
Package availability: 32-pin LQFP.
DESCRIPTION
The PL138-18 family is a high performance low-cost
1: 10 outputs Differential LVPECL fanout buffer.
The family of Differential LVPECL buffers are designed to
operate from a single power supply of 2.5V±5% or 3.3V±10%.
The differential input pairs are designed to accept most
standard input signal levels, using an appropriate resistor bias
network, and produce a high quality set of outputs with the
lowest possible skew on the outputs, which is guaranteed for
part-to-part or lot-to lot skew.
Designed to fit in a small form-factor package, PL138
family offers up to 1GHz of output operation with very
low-power consumption, and lowest additive jitter of any
comparable device. The Output Enable feature, when
activated, allows the IC to consume less than 10µA of
current.
BLOCK DIAGRAM
CLK-IN0
CLK-IN0B
CLK-IN1
CLK-IN1B
CLK_SEL
VBB
0
1
Q9
QB9
Q8
QB8
Q7
QB7
Q6
QB6
Q5
QB5
Q4
QB4
Q3
QB3
Q2
QB2
Q1
QB1
Q0
QB0
32-Pin LQFP Package
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/26/13 Page 1




Micrel

PL138-18 Datasheet Preview

PL138-18 Datasheet

2.5V-3.3V Low-Skew 1:10 Differential PECL Fanout Buffer

No Preview Available !

PL138-18
2.5V-3.3V Low-Skew 1:10 Differential PECL Fanout Buffer
PIN DESCRIPTIONS
Name
Package Pin #
LQFP-32
Vcc 1, 9, 16, 25, 32
CLK_SEL
2
CLK-IN0
3
CLK-IN0B
4
VBB
CLK-IN1
5
6
CLK-IN1B
7
VEE
Q0 ~ Q9
QB0 ~ QB9
8
11, 13, 15, 18, 20,
22, 24, 27, 29, 31
10, 12, 14, 17, 19,
21, 23, 26, 28, 30
Type
P
P
I
I
O
I
I
P
O
O
Description
Power Supply pin connection
Clock select input. See table below for functional spec. and Single
Ended signal interface.
True part of differential clock input signal.
Complementary part of differential clock input signal.
Bias Reference Output
True part of differential clock input signal.
Complementary part of differential clock input signal.
Power Supply pin connection
LVPECL True output
LVPECL Complementary output
INPUT LOGIC BLOCK DIAGRAM
CLK-IN0
CLK-IN0B
CLK-IN1
CLK-IN1B
CLK_SEL
INPUT PIN CHARACTERISTICS
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Min.
Typ.
75
50
Max.
Units
k
k
INPUT CLOCK CONTROL SELECTION
CLK_SEL
0
1
Selected Source
CLK-IN0, CLK-IN0B
CLK-IN1, CLK-IN1B
INPUT CLOCK FUNCTION
Inputs
CLK-IN0 or CLK- CLK-IN0B or CLK-
IN1 IN1B
01
10
0 See page 8 for
1 accepting SE input
Outputs
Q0:Q7 QB0:QB7
Low High
High Low
Low High
High Low
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/26/13 Page 2


Part Number PL138-18
Description 2.5V-3.3V Low-Skew 1:10 Differential PECL Fanout Buffer
Maker Micrel
Total Page 11 Pages
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