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PL133-67 Datasheet Preview

PL133-67 Datasheet

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC

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PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
FE AT UR E S
DESCRIPTION
1:6 LVCMOS output fanout buffer for DC to 150MHz The PL133-67 is an advanced fanout buffer design for
8mA Output Drive Strength
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
high performance, low-power, small form factor applica-
tions. The PL133-67 accepts a reference clock input from
DC to 150MHz and provides 6 outputs of the same fre-
quency.
Low Additive Phase Jitter of 60fs RMS
The PL133-67 is offered in a TSSOP-16L package and it
2.5V to 3.3V, ±10% operation
Operating temperature range from -40°C to 85°C
offers the best phase noise, additive jitter performance,
and lowest power consumption of any comparable IC.
Available in 16-Pin SOP GREEN/RoHS package
The PL133-67 outputs can be disabled to a high imped-
ance (tri-state) by pulling low the OE pin. When the OE pin
is high, the outputs are enabled and follow the REF input
signal. When the OE pin is left open, a pull-up resistor on
the chip will default the OE pin to logic 1 so the outputs are
enabled.
BLOCK DIAGRAM AND PACKAGE PINOUT
REF
OE
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
REF
DNC
CLK0
VDD
GND
CLK1
CLK2
OE^
1
2
3
4
5
6
7
8
16 DNC
15 DNC
14 CLK5
13 VDD
12 GND
11 CLK4
10 CLK3
9 GND
TSSOP-16L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 1




Micrel

PL133-67 Datasheet Preview

PL133-67 Datasheet

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC

No Preview Available !

PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
PIN DESCRIPTIONS
Name
TSSOP-16L
REF
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
VDD
GND
OE
DNC
1
3
6
7
10
11
14
4, 13
5, 9, 12
8
2, 8, 15, 16
Type
I
O
O
O
O
O
O
P
P
I
-
Description
Input reference frequency.
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
VDD connection
GND connection
Output Enable Control Input with 130KPull-Up
Do Not Connect
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB d esign:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1 F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 ohm)
50 ohm line
To CMOS Input
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 2


Part Number PL133-67
Description Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
Maker Micrel
Total Page 6 Pages
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