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PL133-47 Datasheet Preview

PL133-47 Datasheet

Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC

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PL133-47
Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC
FE AT UR E S
1:4 LVCMOS output fanout buffer for DC to150MHz
Low Additive Phase Jitter of 60fs RMS
8mA Output Drive Strength
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
2.5V to 3.3V, ±10% operation
Operating temperature range from -40°C to 85°C
Available in 8-Pin SOP GREEN/RoHS package
DESCRIPTION
The PL133-47 is an advanced fanout buffer design for
high performance, low-power, small form factor applica-
tions. The PL133-47 accepts a reference clock input from
DC to 150MHz and provides 4 outputs of the same fre-
quency.
The PL133-47 is offered in a SOP-8L package and it offers
the best phase noise, additive jitter performance, and low-
est power consumption of any comparable IC.
BLOCK DIAGRAM AND PACKAGE PINOUT
REF
CLK0
CLK1
CLK2
CLK3
VDD
VDD
REF
GND
1
2
3
4
8 CLK3
7 CLK2
6 CLK1
5 CLK0
SOP-8L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/14/1 Page 1




Micrel

PL133-47 Datasheet Preview

PL133-47 Datasheet

Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC

No Preview Available !

PL133-47
Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC
PIN DESCRIPTIONS
Name
SOP-8L
Type
Description
REF
CLK0
CLK1
CLK2
CLK3
VDD
GND
3 I Input reference frequency.
5 O Buffered clock output
6 O Buffered clock output
7 O Buffered clock output
8 O Buffered clock output
1, 2 P VDD connection
4 P GND connection
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB d esign:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid refl ections bouncing
back and forth.
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1 F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 ohm)
50 ohm line
To CMOS Input
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 1/27/11 Page 2


Part Number PL133-47
Description Low-Power 2.25V to 3.63V DC to 150MHz 1:4 Fanout Buffer IC
Maker Micrel
Total Page 7 Pages
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