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PL123-09N Datasheet Preview

PL123-09N Datasheet

Low Skew Fanout Buffer

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FE AT UR E S
Output fanout buffer for DC to 134MHz
Output Options:
o 1:5 output fanout with PL123-05
o 1:9 output fanout with PL123-09
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
Low Additive Phase Jitter of 60fs RMS
2.5V to 3.3V, ±10% operation
1.8V ±10% operation up to 67MHz
Operating temperature range from -40°C to 85°C
Available in 16-Pin SOP (PL123-09) and 8-Pin
SOP (PL123-05). Both are GREEN/RoHS packag-
es.
PL123-05N/-09N
Low Skew Fanout Buffer
DESCRIPTION
The PL123-05N and PL123-09N are a low-cost
fanout buffers for distributing high-speed clocks with
low output to output skew and preserving low noise
properties. The fanout buffers accept an input from
DC to 134MHz and provide 5 or 9 outputs of the same
frequency. A typical PL123-09N application for driving
SDRAM in PC systems would use eight outputs to
drive two DIMMs, or four SO-DIMMs, with the re-
maining output used for driving an external feed-
back to a PLL. A typical PL123-05N application is
to fanout a low noise CMOS clock oscillator to 5
low noise CMOS clocks.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM AND PACKAGE PINOUT
REF
REF
CLK1
CLK2
CLK3
CLK4
CLK5
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
REF
CLK1
CLK2
GND
18
27
36
45
SOP-8L
CLK5
CLK4
VDD
CLK3
REF
CLK1
CLK2
VDD
GND
CLK3
CLK4
VDD
1
2
3
4
5
6
7
8
16 CLK9
15 CLK8
14 CLK7
13 VDD
12 GND
11 CLK6
10 CLK5
9 GND
SOP-16L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/15/12 Page 1




Micrel

PL123-09N Datasheet Preview

PL123-09N Datasheet

Low Skew Fanout Buffer

No Preview Available !

PIN DESCRIPTIONS
Name
PL123-09N
SOP-16L
REF 1
CLK1
2
CLK2
3
VDD 4, 8, 13
GND 5, 9, 12
CLK3
6
CLK4
7
CLK5
10
CLK6
11
CLK7
14
CLK8
15
CLK9
16
PL123-05N
SOP-8L
1
2
3
6
4
5
7
8
-
-
-
-
PL123-05N/-09N
Low Skew Fanout Buffer
Type
I
O
O
P
P
O
O
O
O
O
O
O
Description
Input reference frequency.
Buffered clock output
Buffered clock output
VDD connection
GND connection
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1 F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 ohm)
50 ohm line
To CMOS Input
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 www.micrel.com Rev 03/15/12 Page 2


Part Number PL123-09N
Description Low Skew Fanout Buffer
Maker Micrel
Total Page 8 Pages
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