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MAX9126 - Quad LVDS Line Receivers

This page provides the datasheet information for the MAX9126, a member of the MAX9125 Quad LVDS Line Receivers family.

Description

The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise.

Features

  • integrated parallel termination resistors (nominally 115Ω), which eliminate the requirement for four discrete termination resistors and reduce stub length. The MAX9125 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices support a wide common-mode input range of 0.05V to 2.35V, allowing f.

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Full PDF Text Transcription

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MAX9125/MAX9126 19-1908; Rev 0; 5/01 EVAALVUAAILTAIOBNLEKIT Quad LVDS Line Receivers with Integrated Termination General Description The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100Ω. The transmission media may be printed circuit (PC) board traces or cables. The MAX9125/MAX9126 accept four LVDS differential inputs and translate them to 3.3V CMOS outputs. The MAX9126 features integrated parallel termination resistors (nominally 115Ω), which eliminate the requirement for four discrete termination resistors and reduce stub length.
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