DSSHA1 Datasheet | Maxim Integrated

Description The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the plex SHA-1 putation required for authenticating SHA-1 devices. The DSSHA1 can pute SHA-1 message authentication codes (MACs) for use with Maxim SHA-1 devices, such as the DS1963S, DS1961S, DS28E10, DS28E02, DS2460, DS28CN01, and DS28E01-100. The device can output the 20-byte MAC result from registers required for parison against SHA-1 slave devices. When incorporated into a design, DSSHA1 also provides an offloading function, relieving a microcontroller of performing the SHA-1 putation. Applications Printer Cartridge Authentication Clone Prevention of Systems and PCB Designs License Management Secure Feature Control of Systems Network Appliance Authentication Features - SHA-1 putations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz) - Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process) - Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs - 64-Byte RAM for Message Input - Five 32-Bit Registers to Read MAC Result - Available in Synthesizable Verilog® - Made as a Low-Level Module to be Instantiated by a Top-Level Module - Includes Test Bench Typical Operating Circuit MICROPROCESSOR ASIC- TOP-LEVEL MODULE DSSHA1 MODULE DESIGN MODULE DS1WM MODULE 3.3V R DS28E01-100 Verilog is a registered trademark of Gateway Design Automation Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at .maxim-ic.. Memory-Mapped SHA-1 Coprocessor Description The DSSHA1 is a synthesizable, memory-mapped SHA-1 coprocessor that includes a 64-byte generalpurpose RAM that stores the 64-byte message. The input message is used to pute the SHA-1 MAC. The...