DSSHA1 coprocessor equivalent, memory-mapped sha-1 coprocessor.
* SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz)
* Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process)
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Printer Cartridge Authentication
Clone Prevention of Systems and PCB Designs
License Management
Secure Feature Control o.
The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for au.
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