Datasheet4U Logo Datasheet4U.com

DS2476 - DeepCover Secure Coprocessor

General Description

The DS2476 is a DeepCover® secure ECDSA and HMAC SHA-256 coprocessor companion to the DS28C36.

The coprocessor can compute any required HMACs or ECDSA signatures to do any operation on the DS28C36.

Key Features

  • ECC-256 Compute Engine.
  • FIPS 186 ECDSA P256 Signature and Verification.
  • ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks.
  • ECDSA Authenticated R/W of Configurable Memory.
  • FIPS 180 SHA-256 Compute Engine.
  • HMAC.
  • SHA-256 OTP (One-Time Pad) Encrypted R/W of Configurable Memory Through ECDH Established Key.
  • Two GPIO Pins with Optional Authentication Control.
  • Open-Drain, 4mA/0.4V.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DS2401 Silicon Serial Number Analog Devices
DS2404 EconoRAM Time Chip Dallas Semiconducotr
DS2404S-C01 Dual Port Memory Plus Time Dallas Semiconducotr
DS2407 Dual Addressable Switch Plus 1K.Bit Memory Dallas Semiconducotr
DS2409 MicroLAN Coupler Dallas Semiconducotr

Other Datasheets by Maxim Integrated (now Analog Devices)

Part Number Description
DS2477 DeepCover Secure SHA-3 Coprocessor
DS2401 Silicon Serial Number
DS2405 Addressable Switch
DS2406 Dual Addressable Switch Plus 1Kb Memory
DS2408 1-Wire 8-Channel Addressable Switch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ABRIDGED DATA SHEET Click here for production status of specific part numbers. DS2476 EVALUATION KIT AVAILABLE DeepCover Secure Coprocessor General Description The DS2476 is a DeepCover® secure ECDSA and HMAC SHA-256 coprocessor companion to the DS28C36. The coprocessor can compute any required HMACs or ECDSA signatures to do any operation on the DS28C36. The DS2476 provides a core set of cryptographic tools derived from integrated asymmetric (ECC-P256) and symmetric (SHA-256) security functions. In addition to the security services provided by the hardware implemented crypto engines, the device integrates a FIPS/NIST true random number generator (RNG), 8Kb of secured EEPROM, a decrement-only counter, two pins of configurable GPIO, and a unique 64-bit ROM identification number (ROM ID).