MT28C3212P2
Description
The MT28C3212P2FL and MT28C3212P2NFL bination Flash and SRAM memory devices provide a pact, low-power solution for systems where PCB real estate is at a premium.
Key Features
- Flexible dual-bank architecture
- Asynchronous access time1 Flash access time: 100ns or 110ns @ 1.65V F_VCC SRAM access time: 100ns @ 1.65V S_VCC
- Page Mode read access1 Interpage read access: 100ns/110ns @ 1.65V F_VCC Intrapage read access: 35ns/45ns @ 1.65V F_VCC
- Low power consumption
- Read/Write SRAM during program/erase of Flash
- Dual 64-bit chip protection registers for security purposes
- PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block
- MT28C3212P2NFL only
- Timing 100ns -10 110ns -11
- Boot Block Top T Bottom B
