MT28C3212P2 Overview
2 MEG x 16 PAGE FLASH 128K x 16 SRAM BO MEMORY FLASH AND SRAM BO MEMORY.
MT28C3212P2 Key Features
- Flexible dual-bank architecture
- Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b dur
- Organization: 2,048K x 16 (Flash) 128K x 16 (SRAM)
- Basic configuration: Flash Bank a (4Mb Flash for data storage)
- Eight 4K-word parameter blocks
- Seven 32K-word blocks Bank b (28Mb Flash for program storage)
- Fifty-six 32K-word main blocks SRAM 2Mb SRAM for data storage
- 128K-words
- Asynchronous access time1 Flash access time: 100ns or 110ns @ 1.65V F_VCC SRAM access time: 100ns @ 1.65V S_VCC
- Page Mode read access1 Interpage read access: 100ns/110ns @ 1.65V F_VCC Intrapage read access: 35ns/45ns @ 1.65V F_VCC