Datasheet4U Logo Datasheet4U.com

ispClock5410D - Zero Delay And Fan-Out Buffer

General Description

The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block.

The CleanClock PLL provides an ultra-low-jitter clock source to a set of four V-dividers.

Key Features

  • CleanClock™ PLL.
  • Ultra Low Period Jitter 2.5ps.
  • Ultra Low Phase Jitter 6.5ps.
  • Fully Integrated High-Performance PLL.
  • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback.
  • Up to 10 Programmable Fan-out Buffers.
  • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS.

📥 Download Datasheet

Datasheet Details

Part number ispClock5410D
Manufacturer Lattice Semiconductor
File Size 2.02 MB
Description Zero Delay And Fan-Out Buffer
Datasheet download datasheet ispClock5410D Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2009 Preliminary Data Sheet DS1025 Features CleanClock™ PLL  Ultra Low Period Jitter 2.5ps  Ultra Low Phase Jitter 6.5ps  Fully Integrated High-Performance PLL • • • • • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback  Up to 10 Programmable Fan-out Buffers • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.