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Lattice Semiconductor

ispClock5410D Datasheet Preview

ispClock5410D Datasheet

Zero Delay And Fan-Out Buffer

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ispClock5400D Family
In-System Programmable, Ultra-Low Jitter
Zero Delay and Fan-Out Buffer, Differential
November 2009
Preliminary Data Sheet DS1025
Features
CleanClock™ PLL
Ultra Low Period Jitter 2.5ps
Ultra Low Phase Jitter 6.5ps
Fully Integrated High-Performance PLL
• Programmable lock detect
• Four output dividers
• Programmable on-chip loop filter
• Compatible with Spread Spectrum clocks
• Internal/external feedback
Flexible Clock Reference and External
Feedback Inputs
• Programmable differential input reference/feed-
back standards
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
• Programmable termination
• Clock A/B selection multiplexer
FlexiClock™ I/O
40 MHz to 400 MHz Input/Output Operation
Dual Programmable Skew Per Output
• Programmable phase adjustment
- 16 settings; minimum step size 156 ps
- Up to +/- 9.4 ns skew range
- Coarse and fine adjustment modes
• Programmable time delay adjustment
www.DataSheet4U-.c1o6msettings; 18 ps
Dynamic Skew Control Through I2C
Low Output-to-Output Skew (<100ps)
Up to 10 Programmable Fan-out Buffers
• Programmable differential output standards and
individual enable controls
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
All I/Os are Hot Socket Compliant
Operating Modes
• Fan-out buffer with programmable output skew
control
• Zero delay buffer with dual programmable skew
controls
Dynamic Reconfiguration through I2C
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0° to 70°C) and Industrial (-40°
to 85°C) Temperature Ranges
48-Pin and 64-pin QFNS Packages
Applications
• Low-cost clock source for SERDES
• ATCA, MicroTCA, AMC, PCI Express
• Differential Clock Distribution
• Generic Source Synchronous Clock
Management
• Zero-delay clock buffer
ispClock5400D Family Functional Diagram
I2C
Interface
REFA
REFB
REFSEL
0
1
JTAG
FBK
*Available only in PLL mode.
PLL_BYPASS
Phase
Freq.
Detect
CleanClock PLL
Loop
Filter
VCO
Output
V-Dividers
÷2
0 ÷4
1 ÷8
÷16
Phase Skew
Control
Output
Routing
Matrix
FlexiClock Output Block
Phase
Skew
Control*
Time
Skew
Control T
Differential
Output
Drivers
+
+
+
+
+
+
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1025_01.2




Lattice Semiconductor

ispClock5410D Datasheet Preview

ispClock5410D Datasheet

Zero Delay And Fan-Out Buffer

No Preview Available !

Lattice Semiconductor
ispClock5400D Family Data Sheet
General Description
The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block. The CleanClock PLL pro-
vides an ultra-low-jitter clock source to a set of four V-dividers. The FlexiClock output block receives the clock out-
put from these V-dividers through an output switch matrix and distributes them to the output pin using a
programmable logic interface. There are two members in the ispClock5400D family, the ispClock5410D (10-output
FlexiCLock block) and the ispClock5406D (6-output FlexiClock block). Each of the outputs may be independently
configured to support separate I/O standards (LVDS, LVPECL, SSTL, HSTL, MLVDS, HCSL) and output frequency.
In addition, the skew of each of the outputs can be independently controlled. All configuration information is stored
on-chip in non-volatile E2CMOS® memory.
The ispClock5400D devices provide extremely low propagation delay (zero-delay) from input to output using the
CleanClock PLL. The PLL VCO output clock frequency is divided down by a set of four V- dividers. The output fre-
quencies from these V-dividers, fVCO ÷ 2, fVCO ÷ 4, fVCO ÷ 8 and fVCO ÷ 16 are connected to the output routing
matrix. The output routing matrix enables any output pin to derive its clock from any of the V-dividers outputs. Addi-
tionally, the reference input clock can be connected directly to any output through the output routing matrix.
The FlexiClock block supports dual skew mechanisms: Phase Skew Control and Time Skew Control. These skew
control mechanisms enable fixed output clock skew control during power-up and variable skew during operation.
The ispClock5400D device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The I2C interface can be used to dynamically control the ispClock5400D configuration: Output clock frequency,
Phase Skew, Time skew, Fan-out buffer mode, Output enable.
The core functions of both members of the ispClock5400D family are identical. Table 2-1 summarizes the
ispClock5400D device family.
Table 2-1. ispClock5400D Family
www.DataSheet4U.com
Device
ispClock5410D
ispClock5406D
Number of Programmable
Differential Clock Inputs
2
2
Number of Programmable
Differential Outputs
10
6
2-2


Part Number ispClock5410D
Description Zero Delay And Fan-Out Buffer
Maker Lattice Semiconductor
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