ispClock5406D
Description
The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block. The CleanClock PLL provides an ultra-low-jitter clock source to a set of four V-dividers.
Key Features
- Ultra Low Period Jitter 2.5ps
- Ultra Low Phase Jitter 6.5ps
- Fully Integrated High-Performance PLL * * * *
- Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback
- Up to 10 Programmable Fan-out Buffers
- Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
- Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V
- All I/Os are Hot Socket Compliant
- Operating Modes
- Fan-out buffer with programmable output skew control
