ispClock5400D Datasheet PDF - Lattice Semiconductor Zero Delay And Fan-Out Buffer Specs

ispClock5400D - Zero Delay And Fan-Out Buffer

This page provides the datasheet information for the ispClock5400D, a member of the ispClock5410D Zero Delay And Fan-Out Buffer family.

Datasheet Summary

Description

The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block.

The CleanClock PLL provides an ultra-low-jitter clock source to a set of four V-dividers.

Features

CleanClock™ PLL.
Ultra Low Period Jitter 2.5ps.
Ultra Low Phase Jitter 6.5ps.
Fully Integrated High-Performance PLL.
Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback.
Up to 10 Programmable Fan-out Buffers.
Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS.

Datasheet Details

Part number	ispClock5400D
Manufacturer	Lattice Semiconductor
File Size	2.02 MB
Description	Zero Delay And Fan-Out Buffer
Datasheet	ispClock5400D Datasheet
Additional preview pages of the ispClock5400D datasheet.

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Full PDF Text Transcription

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ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2009 Preliminary Data Sheet DS1025 Features CleanClock™ PLL  Ultra Low Period Jitter 2.5ps  Ultra Low Phase Jitter 6.5ps  Fully Integrated High-Performance PLL • • • • • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback  Up to 10 Programmable Fan-out Buffers • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.

Published: Feb 11, 2010 |