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Lattice Semiconductor

ISPCLOCK5600A Datasheet Preview

ISPCLOCK5600A Datasheet

Clock Generator

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ispClock5600A Family
In-System Programmable, Enhanced Zero-Delay
Clock Generator with Universal Fan-Out Buffer
June 2008
Data Sheet DS1019
Features
8MHz to 400MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak
Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL,
LVDS, LVPECL, Differential HSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (1 to 40)
- Feedback divider (1 to 40)
- Five output dividers (2 to 80)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 156ps
- Locked to VCO frequency
www.DataSheet4UUp.ctoom+/- 12ns skew range
• Coarse and fine adjustment modes
Up to Five Clock Frequency Domains
Flexible Clock Reference and External
Feedback Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, SSTL
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
All Inputs and Outputs are Hot Socket
Compliant
Four User-programmable Profiles Stored in
E2CMOS® Memory
• Supports both test and multiple operating
configurations
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
100-pin and 48-pin TQFP Packages
Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
Product Family Block Diagram
LOCK DETECT
M
* PHASE/
FREQUENCY
FILTER
DETECTOR
N
PLL CORE
Internal/External
Feedback
Select
JTAG
INTERFACE
&
E2CMOS
* MEMORY
* Input Available only on ispClock5620A
BYPASS
MUX
VCO
OUTPUT
DIVIDERS
V0
V1
V2
V3
V4
Multiple Profile
Management Logic
0123
INTERNAL FEEDBACK PATH
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT
ROUTING
MATRIX
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1019_01.4




Lattice Semiconductor

ISPCLOCK5600A Datasheet Preview

ISPCLOCK5600A Datasheet

Clock Generator

No Preview Available !

Lattice Semiconductor
ispClock5600A Family Data Sheet
General Description and Overview
The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen-
erators designed for use in high performance communications and computing applications. The ispClock5610A
provides up to 10 single-ended or five differential clock outputs, while the ispClock5620A provides up to 20 single-
ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate
I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output
provides independent programmable control of termination, slew-rate, and timing skew. All configuration informa-
tion is stored on-chip in non-volatile E2CMOS memory.
The ispClock5600A’s PLL and divider systems supports the synthesis of multiple clock frequencies derived from
the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-
dividers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feed-
back may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/-
pins.
The core functions of all members of the ispClock5600A family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5610A and ispClock5620A.
Table 1-1. ispClock5600A Family Members
Device
ispClock5610A
ispClock5620A
Ref. Input Pairs
1
2
Feedback Input Pairs
1
2
Clock Outputs
10
20
Figure 1-1. ispClock5610A Functional Block Diagram
PS0 PS1
LOCK
RESET
PLL_BYPASS
SGATE GOE OEX OEY
Profile Select
Control
012
3
www.DataSheet4U.com
LOCK
DETECT
REFA+
REFA-
REFVTT
FBKA+
FBKA -
FBKVTT
INPUT
DIVIDER
M
(1-40)
PHASE
DETECT
LOOP
FILTER
N
(1-40)
FEEDBACK
DIVIDER
E2 Configuration
JTAG INTERFACE
OUTPUT ENABLE CONTROLS
VCO
OUTPUT
DIVIDERS
V0
(2-80)
V1
(2-80)
1 V2
0 (2-80)
V3
(2-80)
V4
(2-80)
FEEDBACK
SKEW ADJUST
OUTPUT ROUTING
MATRIX
SKEW
OUTPUT
CONTROL DRIVERS
BANK_0
BANK_0
BANK_1
BANK_1
BANK_2
BANK_2
BANK_3
BANK_3
BANK_4
BANK_4
TDI TMS TCK TDO
1-2


Part Number ISPCLOCK5600A
Description Clock Generator
Maker Lattice Semiconductor
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ISPCLOCK5600A Datasheet PDF






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