ISPCLOCK5600A Datasheet | Lattice Semiconductor

ispClock 5600A Family ™ In-System Programmable, Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer June 2008 Data Sheet DS1019 Features - - - - 8MHz to 400MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak Up to 20 Programmable Fan-out Buffers - Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL - Programmable output impedance - 40 to 70Ω in 5Ω increments - Programmable slew rate - Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V - Up to Five Clock Frequency Domains - Flexible Clock Reference and External Feedback Inputs - Programmable...