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ISPCLOCK5320S - In-System Programmable Zero-Delay

Download the ISPCLOCK5320S datasheet PDF. This datasheet also covers the ISPCLOCK5300S variant, as both devices belong to the same in-system programmable zero-delay family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (ISPCLOCK5300S_LatticeSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ISPCLOCK5320S
Manufacturer Lattice Semiconductor
File Size 1.28 MB
Description In-System Programmable Zero-Delay
Datasheet download datasheet ISPCLOCK5320S Datasheet

Overview

ispClock 5300S Family ™ In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet.

Key Features

  • Four Operating Configurations.
  • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider.
  • Up to +/- 5ns skew range.
  • Coarse and fine adjustment modes.
  • Up to Three Clock Frequency Domains.
  • Flexible Clock Reference and External Feedback Inputs.
  • Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL,.

More Datasheets from Lattice Semiconductor

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