ISPCLOCK5320S - In-System Programmable Zero-Delay

This page provides the datasheet information for the ISPCLOCK5320S, a member of the ISPCLOCK5300S In-System Programmable Zero-Delay family.

Product Overview

Lattice Semiconductor

Part number	ISPCLOCK5320S
Manufacturer	Lattice Semiconductor
File Size	1.28 MB
Description	In-System Programmable Zero-Delay
Datasheet	ISPCLOCK5320S Datasheet
Additional preview pages of the ISPCLOCK5320S datasheet.

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications.

The ispClock5312S, the ﬁrst member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs.

Four Operating Conﬁgurations.
Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider.
Up to +/- 5ns skew range.
Coarse and ﬁne adjustment modes.
Up to Three Clock Frequency Domains.
Flexible Clock Reference and External Feedback Inputs.
Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL,.

Other Datasheets by Lattice Semiconductor

Published: Feb 11, 2010 |