ISPCLOCK5312S, ISPCLOCK5300S - In-System Programmable Zero-Delay

Lattice Semiconductor

Datasheet Details

Part number	ISPCLOCK5312S, ISPCLOCK5300S
Manufacturer	Lattice Semiconductor
File Size	1.28 MB
Description	In-System Programmable Zero-Delay
Datasheet	ISPCLOCK5300S_LatticeSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: ISPCLOCK5312S, ISPCLOCK5300S. Please refer to the document for exact specifications by model.

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications.

Four Operating Conﬁgurations.
Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider.
Up to +/- 5ns skew range.
Coarse and ﬁne adjustment modes.
Up to Three Clock Frequency Domains.
Flexible Clock Reference and External Feedback Inputs.
Programmable single-ended or differential input reference standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL,.

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Published: Feb 11, 2010 |