ISPCLOCK5312S Overview
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVTTL, LVCMOS -3.3V.
ISPCLOCK5312S Key Features
- Four Operating Configurations
- Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divi
- Up to +/- 5ns skew range
- Coarse and fine adjustment modes
- Up to Three Clock Frequency Domains
- Flexible Clock Reference and External Feedback Inputs
- Programmable single-ended or differential input reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL
- Clock A/B selection multiplexer
- Programmable Feedback Standards