LF9501 Datasheet | LOGIC Devices Incorporated

DESCRIPTION The LF9501 is a high-speed, 10-bit programmable line buffer. Some applications the LF9501 is useful for include sample rate conversion, data time pression/expansion, software controlled data alignment, and programmable serial data shifting. By using the MODSEL pin, two different modes of operation can be selected: delay mode and data recirculation mode. The delay mode provides a minimum of 2 to a maximum of 1281 clock cycles of delay between the input and output of the device. The data recirculation mode provides a feedback path from the data output to the data input for use as a programmable circular buffer. By using the length control input (LC10-0) and the length control enable (LCEN) the length of the delay buffer or amount of recirculation delay can be programmed. Providing a delay value on the LC10-0 inputs and driving LCEN LOW will load the delay value into the length control register on the next selected clock edge. Two registers, one preceeding the programmable delay RAM and one following, are included in the delay path. Therefore, the programmed delay value should equal the desired delay minus 2. This consequently means that the value loaded into the length control register must range from 0 to 1279 (to provide an overall range of 2 to 1281). The active edge of the clock input, either positive or negative edge, can be selected with the clock select (CLKSEL) input. All timing is based on the active clock edge selected by CLKSEL. Data can be held temporarily by using the clock enable (CLKEN) input. FEATURES u 50 MHz Maximum Operating Frequency u Programmable Buffer Length from 2 to 1281 Clock Cycles u 10-bit Data Inputs and Outputs u Data Delay and Data Recirculation Modes u Supports Positive or Negative Edge System Clocks u Expandable Data Word Width or Buffer Length u Replaces Harris HSP9501 u 44-pin PLCC, J-Lead LF9501 BLOCK DIAGRAM MODSEL LCO10-0 LCEN REGISTER REGISTER PROGRAMMABLE DELAY RAM DI9-0 REGISTER REGISTER...