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TECHNICAL DATA
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KK7472
AND-Gated J-K Master-Slave FlipFlops with Reset and Clear
LOGIC DIAGRAM
ORDERING INFORMATION KK7472N Plastic KK7472D SOIC TA = -10° to 70° C for all packages
PIN ASSIGNMENT
PIN 14 =VCC PIN 7 = GND NC - No internal connection
FUNCTION TABLE
Inputs Reset L H L H H H H Clear H L L H H H H Clock X X X J X X X L H L H K X X X L L H H Output Q H L H
*
Q L H H* Q0 L H
Q0 H L
TOGGLE
X =don’t care Q0 = the level of Q before the indicated input conditions were established. TOGGLE: Each output changes to the complement of its previous level on each active transition (pulse) of the clock. * This configuration is nonstable; that is, it will not persist whenpreset and clear inputs return to their inactive (high) level.
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KK7472 Datasheet
