iT4032D Datasheet | Iterra

Description The i T4032D is an ultra-wideband phase delay fabricated using 0.1-μm HBT Ga As technology. The high output voltage, excellent rise and fall times, and the high eye diagram quality at all data rates up to 12.5 Gb/s makes the i T4032D suitable for timing adjustment in data and clock distribution at a very high speed. plex digital applications that can benefit from the i T4032D include clock data recovery, edge detectors, NRZ/RZ converters, MUX/DEMUX, and data restoration It is based on an ECL topology in order to guarantee high-speed operation. The device features a single delay element that provides up to 50 ps delay and a 180 deg. shift capability. The delay control can be either differential (using both VCp and VCm) or single-ended (VCp is the active control pad while VCm is shorted to VCref). The nominal control voltage range for the delay is from -2.2 V to -3.0 V, whether the control is single-ended or differential. The flipping control can be either differential (using both VFp and VFn), or single-ended (VFp is the active control pad while VFm is shorted to VCref). The nominal control voltage for the flipping is -2.2 V or -3.0 V whether the control is single-ended or differential. The device is capable of delaying NRZ streams with a data rate up to 12.5 Gb/s or a clock signal with frequency up to 10.7 GHz. The inputs and the outputs are DC coupled. At the input side the internal 50-ohm resistors avoid the need for external impedance matching terminations. The i T4032D uses SCFL I/O levels and is designed so to allow for either single ended or differential data input. .. Features ™ ™ ™ ™ ™ Wideband signal handling: up to 12.5 Gb/s NRZ Delay adjustment: to 50 ps Flipping capability (180 deg. shift) 900 m Vpp typical single-ended output Jitter RMS: <1.5 ps ™ Output rise time (20% - 80 %): <22 ps ™ Output fall time (20% - 80 %): <20 ps ™ 50-ohm matched DC-coupled inputs and outputs ™ Differential or single-ended I/O ™ Power consumption: 1.15 W Device...