Datasheet4U Logo Datasheet4U.com

HCTS27MS - Radiation Hardened Triple 3-Input NOR Gate

Description

The Intersil HCTS27MS is a Radiation Hardened Triple 3-Input NOR Gate.

A Low on all inputs forces the output to a High state.

The HCTS27MS utilizes advanced CMOS/SOS technology to achieve high-speed operation.

Features

  • 3 Micron Radiation Hardened SOS CMOS.
  • Total Dose 200K RAD (Si).
  • SEP Effective LET No Upsets: >100 MEV-cm2/mg.
  • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ).
  • Dose Rate Survivability: >1 x 1012 RAD (Si)/s.
  • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse.
  • Latch-Up Free Under Any Conditions.
  • Military Temperature Range: -55 oC to +125oC GND 7.
  • Significant Power Reduction Compared to LSTTL ICs.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HCTS20MS Radiation Hardened Dual 4-Input NAND Gate Intersil
HCTS164MS 8-Bit Serial-In/Parallel-Out Shift Register Intersil
HCTS191MS Synchronous 4-Bit Up/Down Counter Intersil
HCTSM80101AAL High Clearance and Creepage Distance Transformers BOURNS
HCTSM80102AAL High Clearance and Creepage Distance Transformers BOURNS

Other Datasheets by Intersil (Renesas)

Part Number Description
HCTS273MS Radiation Hardened Octal D Flip-Flop
HCTS21MS Radiation Hardened Dual 4-Input AND Gate
HCTS240AMS Radiation Hardened Octal Buffer/Line Driver/ Three-State
HCTS244MS Radiation Hardened Octal Buffer/Line Driver
HCTS244T Radiation Hardened Octal Buffer/Line Driver/ Three-State

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HCTS27MS September 1995 Radiation Hardened Triple 3-Input NOR Gate Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14 TOP VIEW A1 1 B1 2 A2 3 B2 4 C2 5 Y2 6 14 VCC 13 C1 12 Y1 11 C3 10 B3 9 A3 8 Y3 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55 oC to +125oC GND 7 • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.
Published: |