HCTS27MS Datasheet | Intersil

Features - 3 Micron Radiation Hardened SOS CMOS - Total Dose 200K RAD (Si) - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) - Dose Rate Survivability: >1 x 1012 RAD (Si)/s - Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse - Latch-Up Free Under Any Conditions - Military Temperature Range: -55 o C to +125o C GND 7 - Significant Power Reduction pared to LSTTL ICs - DC Operating Voltage Range: 4.5V to 5.5V - LSTTL Input patibility - VIL = 0.8V Max - VIH = VCC/2 Min - Input Current Levels Ii ≤ 5µA at VOL, VOH 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14 TOP VIEW A1 B1 A2 B2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC C1 Y1 C3 B3 A3 Y3 Description The Intersil HCTS27MS is a Radiation Hardened Triple 3-Input NOR Gate. A Low on all inputs forces the output to a High state. The HCTS27MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS27MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). C2 Y2 GND Functional Diagram An Bn Yn Ordering Information PART NUMBER HCTS27DMSR TEMPERATURE RANGE -55o C to +125o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent PACKAGE 14 Lead SBDIP An 14 Lead Ceramic Flatpack 14 Lead SBDIP L L L HCTS27D/ Sample HCTS27K/ Sample +25o C Sample L H +25o C Sample 14 Lead Ceramic Flatpack Die H H H Cn TRUTH TABLE INPUTS Bn L L H H L L H H Cn L H L H L H L H OUTPUTS Yn H L L L L L L DB NA...