CDP1854 Datasheet | Intersil

CDP1854A, CDP1854AC March 1997 Programmable Universal Asynchronous Receiver/Transmitter (UART) Description The CDP1854A and CDP1854AC are silicon-gate CMOS Universal Asynchronous Receiver/Transmitter (UART) circuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel output data and parallel input data to serial output data. The CDP1854A UART can be programmed to operate in one of two modes by using the mode control input. When the input is high (MODE = 1), the CDP1854A is directly patible with the CDP1800-series microprocessor system without additional interface circuitry. When the mode input is low (MODE = 0), the device is functionally patible with industry standard UART’s such as the TR1602A and CDP6402. It is also pin patible with these types, except that pin 2 is used for the mode control input. The CDP1854A and the CDP1854AC are functionally identical. The CDP1854A has a remended operating voltage range of 4V to 10.5V, and the CDP1854AC has a remended operating voltage range of 4V to 6.5V. Features - Two Operating Modes - Mode 0 - Functionally patible with Industry Types Such as the TR1602A and CDP6402 - Mode 1 - Interfaces Directly with CDP1800-Series Microprocessors without Additional ponents - Full or Half Duplex Operation - Parity, Framing and Overrun Error Detection - Baud Rate - DC to 200K Bits/s at VDD - - - - 5V - DC to 400K Bits/s at VDD - - - - 10V - Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits - False Start Bit Detection Ordering...