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Intersil Electronic Components Datasheet

CDP1853 Datasheet

N-Bit 1 of 8 Decoder

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CDP1853,
CDP1853C
March 1997
N-Bit 1 of 8 Decoder
Features
• Provides Direct Control of Up to 7 Input and 7 Output
Devices
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
PACKAGE TEMP. RANGE
5V
PKG.
10V NO.
PDIP
-40oC to +85oC CDP1853CE CDP1853E E16.3
Burn-In
SBDIP
CDP1853CEX - E16.3
-40oC to +85oC CDP1853CD CDP1853D D16.3
Burn-In
CDP1853CDX - D16.3
Description
The CDP1853 and CDP1853C are 1 of 8 decoders designed for
use in general purpose microprocessor systems. These
devices, which are functionally identical, are specifically
designed for use as gated N-bit decoders and interface directly
with the 1800-series microprocessors without additional compo-
nents. The CDP1853 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1853C has a recommended
operating voltage range of 4V to 6.5V.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low tran-
sition) to the trailing edge of CLOCK B (high-to-low transition).
All outputs will be low when the device is not selected (CE = 0)
and during conditions of CLOCK A and CLOCK B as shown in
Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and
CLOCK B are connected to an 1800-series microprocessor out-
puts N0, N1, N2, TPA, and TPB respectively, when used to
decode I/O commands as shown in Figure 5. The CHIP
ENABLE (CE) input provides the capability for multiple levels of
decoding as shown in Figure 6.
The CDP1853 can also be used as a general 1 of 8 decoder for
I/O and memory system applications as shown in Figure 4.
The CDP1853 and CDP1853C are supplied in hermetic 16-lead
dual-in-line ceramic (D suffix) and plastic (E suffix) packages.
Pinout
16 LEAD DIP
TOP VIEW
CLK A 1
N0 2
N1 3
OUT 0 4
OUT 1 5
OUT 2 6
OUT 3 7
VSS 8
16 VDD
15 CLK B
14 N2
13 CE
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
CDP1853 Functional Diagram
2
N0
3
N1
14
N2
13
CE
1 OF 8
DECODER
EN
4
OUT 0
5 OUT 1
6 OUT 2
7
OUT 3
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
1
CLOCK
A
(TPA)
Qn
15
CLOCK
B
(TPB)
FIGURE 1.
TRUTH TABLE
CE
CL A
CL B
EN
1 0 0 Qn-1
1011
1100
1111
0XX0
N2 N1 N0 EN 0 1 2 3 4 5 6 7
0 0 0 1 10000000
0 0 1 1 01000000
0 1 0 1 00100000
0 1 1 1 00010000
1 0 0 1 00001000
1 0 1 1 00000100
1 1 0 1 00000010
1 1 1 1 00000001
X X X 0 00000000
1 = High level, 0 = Low level, X = Don’t care
Qn-1 = Enable remains in previous state.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-35
File Number 1189.2


Intersil Electronic Components Datasheet

CDP1853 Datasheet

N-Bit 1 of 8 Decoder

No Preview Available !

CDP1853, CDP1853C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All voltage values referenced to VSS terminal)
CDP1853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W)
θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
85
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Operating Temperature Range (TA)
Ceramic Packages (D Suffix Types) . . . . . . . . . . -55oC to +125oC
Plastic Packages (E Suffix Types) . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265oC
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications At TA = -40 to +85oC, Unless Otherwise Specified
CONDITIONS
LIMITS
CDP1853
CDP1853C
PARAMETER
VO VIN VDD
(NOTE1)
(NOTE1)
(V) (V) (V) MIN TYP MAX MIN TYP MAX UNITS
Quiescent Device
Current
IL -
-
-5-
- 10 -
1 10 -
10 100 -
5 50 µA
- - µA
Output Low Drive (Sink) IOL 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA
Current
0.5 0, 10 10
2.6
5.2
-
-
- - mA
Output High Drive
(Source) Current
IOH
4.6
0, 5
5 -1.15
-2.3
9.5 0, 10 10 -2.6
-5.2
- -1.15 -2.3
--
-
- mA
- mA
Output Voltage Low Level
(Note 2)
VOL
- 0, 5 5
- 0, 10 10
-
-
0 0.1 -
0 0.1 -
0 0.1 V
- -V
Output Voltage High Level VOH - 0, 5 5 4.9 5 - 4.9 5 - V
-
0, 10 10
9.9
10
-
-
- -V
Input Low Voltage
VIL 0.5, 4.5
-
5
-
1, 9 - 10 -
- 1.5 -
- 3-
- 1.5 V
- -V
Input High Voltage
VIH 0.5, 4.5
-
5 3.5
-
- 3.5
-
-V
1, 9 - 10 7
- --
- -V
Input Leakage Current
IIN Any 0, 5 5
Input
0, 10 10
-
-
- ±1 -
- ±1 -
- ±1 µA
- - µA
Operating Current
(Note 3)
IDD1
0, 5
0, 5
5
0, 10 0, 10 10
-
-
50 100
150 300
-
-
50 100 µA
- - µA
Input Capacitance
CIN -
---
5 7.5 -
Output Capacitance
COUT
-
---
10 15 -
NOTES:
1. Typical values are for TA = +25oC and nominal voltage.
2. IOL = IOH = 1µA
3. Operating current measured in a CDP1802 system at 2MHz with outputs floating.
5 7.5 pF
10 15 pF
4-36
Spec Number


Part Number CDP1853
Description N-Bit 1 of 8 Decoder
Maker Intersil Corporation
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CDP1853 Datasheet PDF






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