CDP1822C3 Datasheet | Intersil

Description The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in mon Input/Output systems. The Output Disable input allows this RAM to be used in mon data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. Features - For Applications in Aerospace, Military, and Critical Industrial Equipment - Interfaces Directly with CDP1802 Microprocessor - Very Low Operating Current - At VDD = 5V and Cycle Time = 1µs - . 4m A (Typ) - Static CMOS Silicon-On-Sapphire Circuitry - CD4000 Series patible - Industry Standard Pinout - Two Chip Select Inputs - Simple Memory Expansion - Memory Retention for Standby- - . . . 2V (Min) Battery Voltage - Single Power Supply Operation - - 4V to 6.5V - High Noise Immunity 30% of VDD- . . . . 4V to 6.5V - Output Disable for mon I/O Systems - Three-State Data Output for Bus Oriented Systems - Separate Data Inputs and Outputs - Latch-Up-Free Transient Radiation Tolerance Ordering Information PACKAGE SBDIP TEMP. RANGE -55o C to +125o C PART NUMBER CDP1822CD3 PKG. NO. D22.4A Pinout CDP1822C/3 (SBDIP) TOP VIEW A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 VSS 8 DI1 9 DO1 10 DI2 11 22 VDD 21 A4 20...