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CDP1822C - High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM

General Description

The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable.

Key Features

  • high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in common Input/Output systems. The Output Disable input allows this RAM to be used in common data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The.

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CDP1822C 256-Word by 4-Bit LSI Static Random-Access Memory GE
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Other Datasheets by Intersil (now Renesas)

Part Number Description
CDP1822C3 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM
CDP1822 256-Word x 4-Bit LSI Static RAM
CDP1821C High-Reliability CMOS 1024-Word x 1-Bit Static RAM
CDP1821C3 High-Reliability CMOS 1024-Word x 1-Bit Static RAM
CDP1823 128-Word x 8-Bit LSI Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDP1822C/3 March 1997 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM Description The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in common Input/Output systems. The Output Disable input allows this RAM to be used in common data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition.