CDP1020 Datasheet | Intersil

Data Sheet April 1999 File Number SMBus/I 2C ACPI Dual Device Bay Controller The CDP1020 is an ACPI pliant Device Bay Controller (DBC) that can control two device bays. The controller interfaces to the host system through the industry standard I2C or System Management Bus (SMBus) and is fully pliant with Device Bay Specification 0.90. The CDP1020 is designed to be patible with the integrated SMBus host controller of the Pii X4/Pii X6 in Intel Architecture platforms. The CDP1020 is designed to be placed on the host motherboard, on a riser, or adjacent to the Device Bay connectors. The required clock source is generated from an internal oscillator on the CLK pin, with an external RC to set the frequency. This lowers the system cost and allows the CDP1020 to remain active during S3-S5 system states where all clock generators have been stopped. One of the key Features of this device is the on-chip level shifters that provide slew rate controlled, direct gate drive for external N-Channel MOSFETs (Intersil HUF76113DK8 remended) to switch the device bay VID supplies. Switching an N-Channel device as opposed to a P-Channel reduces both device cost and device count, resulting in an overall lower system cost. Configuration data for the CDP1020, including subsystem vendor ID, subsystem revision, bay size and device bay capabilities are designed to be written into the CDP1020 by the system BIOS at power up. The registers for this data are write-once-only and thus bee read-only after the initial BIOS write. The address selection pins (AD1 and AD0) allow the CDP1020 to occupy any one of four I2C/SMBus addresses. This enables up to four CDP1020 devices to coexist in a system. The CDP1020 implements high current outputs for direct drive (with a limiting resistor) of the optional bay status LEDs. These indicators are two color (green/amber) mon anode or anti-parallel LEDs that indicate the device bay status per the Device Bay Specification...