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Intersil Electronic Components Datasheet

CDP1020 Datasheet

SMBus/I2C ACPI Dual Device Bay Controller

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CDP1020
Data Sheet
April 1999
File Number 4704
SMBus/I2C ACPI Dual Device Bay
Controller
The CDP1020 is an ACPI compliant Device Bay Controller
(DBC) that can control two device bays. The controller
interfaces to the host system through the industry standard
I2C or System Management Bus (SMBus) and is fully
compliant with Device Bay Specification 0.90. The CDP1020
is designed to be compatible with the integrated SMBus host
controller of the PiiX4/PiiX6 in Intel Architecture platforms.
The CDP1020 is designed to be placed on the host
motherboard, on a riser, or adjacent to the Device Bay
connectors. The required clock source is generated from an
internal oscillator on the CLK pin, with an external RC to set
the frequency. This lowers the system cost and allows the
CDP1020 to remain active during S3-S5 system states
where all clock generators have been stopped.
One of the key features of this device is the on-chip level
shifters that provide slew rate controlled, direct gate drive for
external N-Channel MOSFETs (Intersil HUF76113DK8
recommended) to switch the device bay VID supplies.
Switching an N-Channel device as opposed to a P-Channel
reduces both device cost and device count, resulting in an
overall lower system cost.
Configuration data for the CDP1020, including subsystem
vendor ID, subsystem revision, bay size and device bay
capabilities are designed to be written into the CDP1020 by
the system BIOS at power up. The registers for this data are
write-once-only and thus become read-only after the initial
BIOS write.
The address selection pins (AD1 and AD0) allow the
CDP1020 to occupy any one of four I2C/SMBus addresses.
This enables up to four CDP1020 devices to coexist in a
system.
The CDP1020 implements high current outputs for direct
drive (with a limiting resistor) of the optional bay status
LEDs. These indicators are two color (green/amber)
common anode or anti-parallel LEDs that indicate the device
bay status per the Device Bay Specification 0.90.
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC) PACKAGE
CDP1020
0 to 85
28 Ld SOIC
PKG. NO.
M28.3
For More Information Contact:
Mike Coletta (714) 433-0600
Terry Pierce (407) 729-5835
Features
• Fully Compliant with Device Bay Specification 0.90 and
ACPI Specification 1.0
• Industry Standard SMBus/I2C Interface
• Controls for Two Device Bays
• Onboard Level Shifting for Direct Drive of N-Channel
MOSFET VID Switches
• Integrated Pull-up Resistors on 1394PRx, USBPRx,
SECUREx, and REMREQx Inputs
• RC Type Oscillator - Low Cost and Low Power
Consumption
• Operational Voltage from 3.3 to 5.5V
• “5V Tolerant” Inputs at all Operating Voltages
• Write-Once BIOS/External Configuration
• Removal Request Input for Each Bay
• Security Lock Input for Each Bay
• High Current Device Bay LED Indicator Drivers With
Separate High-Side Power Input
• Configurable Level/Pulse Bay Solenoid Drivers
• Programmable Insertion Time Out Delay
• HCMOS Technology; 28 Lead Plastic SOIC
Pinout
CDP1020 (SOIC)
TOP VIEW
RESET 1
TEST (VDD) 2
1394PR0 3
USBPR0 4
REMREQ0 5
SECURE0 6
1394PR1 7
USBPR1 8
REMREQ1 9
SECURE1 10
SDA 11
SCK 12
ALRT 13
VGATE 14
28 AD1
27 AD0
26 CLK
25 VSS
24 VDD
23 VLED
22 LEDA1
21 LEDG1
20 LEDA0
19 LEDG0
18 SFTLOCK1
17 SFTLOCK0
16 PWREN1
15 PWREN0
2-418
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999


Intersil Electronic Components Datasheet

CDP1020 Datasheet

SMBus/I2C ACPI Dual Device Bay Controller

No Preview Available !

CDP1020
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
RESET
TEST
1394PR0
USBPR0
REMREQ0
SECURE0
1394PR1
USBPR1
REMREQ1
SECURE1
SDA
SCK
ALRT
VGATE
PWREN0
PWREN1
SFTLOCK0
SFTLOCK1
LEDG0
LEDA0
LEDG1
LEDA1
VLED
VDD
VSS
CLK
AD0
AD1
Block Diagram
RESET
IN/OUT
IN
-
IN
IN
IN
IN
IN
IN
IN
IN
IN/OUT
IN/OUT
OUT
-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
-
-
-
IN
IN
IN
AD1
AD0
SCK
SDA
ALRT
I 2C/SMBus
INTERFACE
1394PR0
USBPR0
REMREQ0
SECURE0
LEDA0
LEDG0
PWREN0
SFTLOCK0
VLED
VGATE
DEBOUNCE
LOGIC and
PULLUP Rs
TIMER/
LEVEL
SHIFTER
LEVEL
SHIFT
PIN DESCRIPTION
Device Bay Controller Master Reset Schmitt Input
Test pin used by manufacturer only. Must be externally connected to VDD
Bay 0 1394 Presence Input with Active Pull-up
Bay 0 USB Presence Input with Active Pull-up
Bay 0 Remove Request Input with Active Pull-up
Bay 0 Security Input with Active Pull-up
Bay 1 1394 Presence Input with Active Pull-up
Bay 1 USB Presence Input with Active Pull-up
Bay 1 Remove Request Input with Active Pull-up
Bay 1 Security Input with Active Pull-up
SMBus/I2C Data Schmitt Input/Open-Drain Output
SMBus/I2C Clock Schmitt Input/Open-Drain Output
SMBus Alert Open-Drain Output
Power Supply Input for PWREN0/PWREN1 Drivers
Bay 0 Power Enable 12V NMOS Gate Drive Output
Bay 1 Power Enable 12V NMOS Gate Drive Output
Bay 0 Software Controlled Lock Mechanism Driver
Bay 1 Software Controlled Lock Mechanism Driver
Bay 0 Status Indicator (Green LED) Driver
Bay 0 Status Indicator (Amber LED) Driver
Bay 1 Status Indicator (Green LED) Driver
Bay 1 Status Indicator (Amber LED) Driver
Power Supply Input for LED Driver (LEDAx, LEDGx)
Power Supply Input (Power)
Power Supply Return (Ground or GND)
External Clock Schmitt Input (for RC oscillator)
SMBus/I2C Address Configuration Bit 0
SMBus/I2C Address Configuration Bit 1
DEVICE BAY
CONTROLLER LOGIC
BSTR0 - $10
BCER0 - $14
BSTR1 - $18
BCER1 - $1C
OSCILLATOR
CIRCUITRY
VENDOR - $00
REVISION - $04
SUBSYS VENDOR - $08
SUBSYS REV- $0A
DBCCR - $0C
SFR - $FC
DEBOUNCE
LOGIC and
PULLUP Rs
TIMER/
LEVEL
SHIFTER
CLK
1394PR1
USBPR1
REMREQ1
SECURE1
LEDA1
LEDG1
LEVEL
SHIFT
PWREN1
SFTLOCK1
VLED
VGATE
2-419


Part Number CDP1020
Description SMBus/I2C ACPI Dual Device Bay Controller
Maker Intersil Corporation
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CDP1020 Datasheet PDF






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Intersil Corporation





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