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Intersil Electronic Components Datasheet

CD4556BMS Datasheet

CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers

No Preview Available !

December 1992
CD4555BMS
CD4556BMS
CMOS Dual Binary to 1 of 4
Decoder/Demultiplexers
Features
• High Voltage Type (20V Rating)
• CD4555BMS: Outputs High on Select
• CD4556BMS: Outputs Low on Select
• Expandable with Multiple Packages
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Decoding
• Code Conversion
• Demultiplexing (Using Enable Input as a Data Input
• Memory Chip-Enable Selection
• Function Selection
Description
CD4555BMS and CD4556BMS are dual one-of-four decod-
ers/demultiplexers. Each decoder has two select inputs (A
and B), an Enable input (E), and four mutually exclusive out-
puts. On the CD4555BMS the outputs are high on select; on
the CD4556BMS the outputs are low on select.
When the Enable input is high, the outputs of the
CD4555BMS remain low and the outputs of the
CD4556BMS remain high regardless of the state of the
select inputs A and B. The CD4555BMS and CD4556BMS
are similar to types MC14555 and MC14556, respectively.
The CD4555BMS and CD4556BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4555B Only
*H46 †H4T
H1E
H6W
†CD4556B Only
Pinouts
CD4556BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
CD4555BMS
TOP VIEW
E1
A2
B3
1/2 OF DUAL Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
16 VDD
15 E
14 A
13 B
12 Q0 1/2 OF DUAL
11 Q1
10 Q2
9 Q3
Functional Diagrams
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
VSS 8
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
CD4555BMS
VDD 16
A
B
2
3
E1
A 14
B 13
E 15
4 Q0
5 Q1
6 Q2
7 Q3
12 Q0
11 Q1
10 Q2
9 Q3
VSS 8
CD4556BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1249
File Number 3346


Intersil Electronic Components Datasheet

CD4556BMS Datasheet

CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers

No Preview Available !

Specifications CD4555BMS, CD4556BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1250


Part Number CD4556BMS
Description CMOS Dual Binary to 1 of 4 Decoder/Demultiplexers
Maker Intersil Corporation
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CD4556BMS Datasheet PDF






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