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Intersil Electronic Components Datasheet

CD4517BMS Datasheet

CMOS Dual 64-Stage Static Shift Register

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CD4517BMS
December 1992
CMOS Dual 64-Stage
Static Shift Register
Features
Description
• High-Voltage Types (20-Volt Rating)
• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V
• Clock Frequency 12MHz (Typ.) at VDD = 10V
• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock
Rise and Fall Times
• Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load, or Two HTL Loads
• 3-State Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V, and 15V Parametric Ratings
• Meets all Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ‘B’ Series CMOS
Devices"
Applications
• Time-delay Circuits
CD4517BMS dual 64-stage static shift
register consists of two independent registers
each having a clock, data, and write enable
input and outputs accessible at taps following
the 16th, 32rd, 48th, and 64th stages. These
taps also serve as input points allowing data
to be inputted at the 17th, 33rd, and 49th
stages when the write enable input is a logic
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
opeation of the CD4517BMS. Inputs at the
intermediate taps allow entry of 64 bits into
the register with 16 clock pulses. The 3-state
outputs permit connection of this device to an
external bus.
The CD4517BMS is supplied in these 16 lead
outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6P
• Scratch-pad Memories
• General-purpose Serial Shift-register Applications
Pinout
CD4517BMS
TOP VIEW
Q16A 1
Q48A 2
WEA 3
CLA 4
Q64A 5
Q32A 6
DA 7
VSS 8
16 VDD
15 Q16B
14 Q48B
13 WEB
12 CLB
11 Q64B
10 Q32B
9 DB
Functional Diagram
CL
CL
Q16
D D1
16 STAGES
CL
Q32
D17
16 STAGES
WE = 0
WE = 1
WE
CL
Q48
D33
16 STAGES
CL
Q64
D49
16 STAGES
STAGE 16
OUT/IN TAP
STAGE32
OUT/IN TAP
STAGE 48
OUT/IN TAP
STAGE 64
OUT/IN TAP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1197
File Number 3341


Intersil Electronic Components Datasheet

CD4517BMS Datasheet

CMOS Dual 64-Stage Static Shift Register

No Preview Available !

Specifications CD4517BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
Tri-State Output
Leakage
IOZL VIN = VDD or GND VDD = 20V
VOUT = 0V
1
2
+25oC
+125oC
-0.4 - µA
-12 - µA
VDD = 18V
3
-55oC
-0.4 - µA
Tri-State Output
Leakage
IOZH VIN = VDD or GND VDD = 20V
VOUT = VDD
1
2
+25oC
+125oC
- 0.4 µA
- 12 µA
VDD = 18V
3
-55oC
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1198


Part Number CD4517BMS
Description CMOS Dual 64-Stage Static Shift Register
Maker Intersil Corporation
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CD4517BMS Datasheet PDF






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