CD4517BMS
Description
CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages.
Key Features
- High-Voltage Types (20-Volt Rating)
- Low Quiescent Current
- 10nA/pkg (Typ.) at VDD = 5V
- Clock Frequency 12MHz (Typ.) at VDD = 10V
- Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock Rise and Fall Times
- Capable of Driving Two Low-power TTL Loads, One Low-power Schottky TTL Load, or Two HTL Loads
- 3-State Outputs
- 100% Tested for Quiescent Current at 20V
- Standardized, Symmetrical Output Characteristics
- Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ‘B’ Series CMOS Devices"
