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Intersil Electronic Components Datasheet

CD4512BMS Datasheet

CMOS Dual 4-Bit Latch

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CD4512BMS
December 1992
CMOS Dual 4-Bit Latch
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• 3-State Outputs
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
CD4512BMS
TOP VIEW
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
VSS 8
16 VDD
15 3-STATE DISABLE
14 SEL. OUTPUT
13 C
12 B
11 A
10 INHIBIT
9 D7
Functional Diagram
Applications
• Digital Multiplexing
• Number-sequence Generation
• Signal Gating
Description
CD4512BMS is an 8-channel data selector featuring a three-
state output that can interface directly with, and drive, data
lines of bus-oriented systems.
The CD4512BMS is supplied in these 16 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4S
H1E
H3X
3-STATE DISABLE
INHIBIT
10 15
D0-1
D1-2
CHANNELS
INPUTS
D2-3
D3-4
D4-5
SELECT
CONTROL
D5-6
D6-7
D7-9
A-11
B-12
C-13
CD4512BMS
14 SELECT
OUTPUT
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1180
File Number 3340


Intersil Electronic Components Datasheet

CD4512BMS Datasheet

CMOS Dual 4-Bit Latch

No Preview Available !

Specifications CD4512BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
Tri-State Output
Leakage
IOZL VIN = VDD or GND VDD = 20V
VOUT = 0V
1
2
+25oC
+125oC
-0.4 - µA
-12 - µA
VDD = 18V
3
-55oC
-0.4 - µA
Tri-State Output
Leakage
IOZH VIN = VDD or GND VDD = 20V
VOUT = VDD
1
2
+25oC
+125oC
- 0.4 µA
- 12 µA
VDD = 18V
3
-55oC
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1181


Part Number CD4512BMS
Description CMOS Dual 4-Bit Latch
Maker Intersil Corporation
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CD4512BMS Datasheet PDF






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