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Intersil Electronic Components Datasheet

CD4508BMS Datasheet

CMOS Dual 4-Bit Latch

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CD4508BMS
December 1992
CMOS Dual 4-Bit Latch
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• Two Independent 4-Bit Latches
CD4508BMS
TOP VIEW
• Individual Master Reset for Each 4-Bit Latch
• 3-State Outputs with High-Impedance State for Bus
Line Applications
• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)
at VDD = 10V and CL = 50pF
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Applications
• Buffer Storage
• Holding Registers
• Data Storage and Multiplexing
Description
CD4508BMS dual 4-bit latch contains two identical 4-bit
latches with separate STROBE, RESET, and OUTPUT
DISABLE controls. With the STROBE line in the high state,
the data on the "D" inputs appear at the corresponding "Q"
outputs provided the DISABLE line is in the low state.
Changing the STROBE line to the low state locks the data
into the latch. A high on the reset line forces the outputs to a
low level regardless of the state of the STROBE input. The
outputs are forced to the high-impedance state for bus line
applications by a high level on the DISABLE input.
RESET A 1
STROBE A 2
OUTPUT DISABLE A 3
D0A 4
Q0A 5
D1A 6
Q1A 7
D2A 8
Q2A 9
D3A 10
Q3A 11
VSS 12
Functional Diagram
OUTPUT
DISABLE
D0A
D1A
D2A
D3A
STROBE
RESET
OUTPUT
DISABLE
D0B
D1B
D2B
D3B
STROBE
RESET
4-BIT
LATCH
4-BIT
LATCH
24 VDD
23 Q3B
22 D3B
21 Q2B
20 D2B
19 Q1B
18 D1B
17 Q0B
16 D0B
15 OUTPUT DISABLE B
14 STROBE B
13 RESET B
3-STATE
OUTUTS
Q0A
Q1A
Q2A
Q3A
3-STATE
OUTUTS
Q0B
Q1B
Q2B
Q3B
The CD4508BMS is supplied in these 24 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1Z
H4P
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1148
File Number 3337


Intersil Electronic Components Datasheet

CD4508BMS Datasheet

CMOS Dual 4-Bit Latch

No Preview Available !

Specifications CD4508BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
Tri-State Output
Leakage
IOZL VIN = VDD or GND VDD = 20V
VOUT = 0V
1
2
+25oC
+125oC
-0.4 - µA
-12 - µA
VDD = 18V
3
-55oC
-0.4 - µA
Tri-State Output
Leakage
IOZH VIN = VDD or GND VDD = 20V
VOUT = VDD
1
2
+25oC
+125oC
- 0.4 µA
- 12 µA
VDD = 18V
3
-55oC
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1149


Part Number CD4508BMS
Description CMOS Dual 4-Bit Latch
Maker Intersil Corporation
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CD4508BMS Datasheet PDF






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