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CD4502BMS - CMOS Strobed Hex Inverter/Buffer

General Description

of ‘B’ Series CMOS Devices” D3 Q3 D1 1 2 3 16 VDD 15 D6 14 Q6 13 D5 12 INHIBIT 11 Q5 10 D4 9 Q4 3 STATE 4 OUTPUT DISABLE Q1 5 D2 Q2 VSS 6 7 8 Functional Diagram 3 STATE 4 OUTPUT DISABLE 12 INHIBIT 3 D1 D2 6 Applications 3 State Hex Inverter for Interfacing ICs with Data Buses

Key Features

  • High Voltage Type (20V Rating).
  • 2 TTL Load Output Drive Capability.
  • 3 State Outputs.
  • Common Output Disable Control.
  • Inhibit Control.
  • 100% Tested for Quiescent Current at 20V.
  • 5V, 10V and 15V Parametric Ratings.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4502BMS December 1992 CMOS Strobed Hex Inverter/Buffer Pinout CD4502BMS TOP VIEW Features • High Voltage Type (20V Rating) • 2 TTL Load Output Drive Capability • 3 State Outputs • Common Output Disable Control • Inhibit Control • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No.