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Intersil Electronic Components Datasheet

CD4094BMS Datasheet

CMOS 8-Stage Shift-and-Store Bus Register

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CD4094BMS
December 1992
CMOS 8-Stage Shift-and-Store
Bus Register
Features
Pinout
• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common
Bus
• Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading
• Medium Speed Operation - 5MHz at 10V (typ)
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4094BMS
TOP VIEW
STROBE 1
DATA 2
CLOCK 3
Q1 4
Q2 5
Q3 6
Q4 7
VSS 8
16 VDD
15 OUTPUT ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
10 Q’S
9 QS
Functional Diagram
Applications
• Serial-to-Parallel Data Conversion
• Remote Control Holding Register
• Dual-Rank Shift, Hold, and Bus Applications
SERIAL
OUTPUTS
DATA
2
10 Q’S
8-STAGE
CLOCK 3
SHIFT
9 QS
REGISTER
Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs when-
ever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed opera-
tion in cascaded systems in which the clock rise time is fast. The
same serial information, available at the Q’S terminal on the next
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow.
The CD4094BMS is supplied in these 16 lead outline packages:
STROBE 1
8-BIT
STORAGE
REGISTER
OUTPUT
ENABLE 15
3-STATE
OUTPUTS
VDD = 16
VSS = 8
PARALLEL OUTPUTS Q1 - Q8
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
Braze Seal DIP H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1083
File Number 3194


Intersil Electronic Components Datasheet

CD4094BMS Datasheet

CMOS 8-Stage Shift-and-Store Bus Register

No Preview Available !

Specifications CD4094BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
7
+25oC
VOH > VOL < V
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
(Note 2)
Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
(Note 2)
Input Voltage Low
VIL VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC -
4V
(Note 2)
VOL < 1.5V
Input Voltage High
VIH VDD = 15V, VOH > 13.5V,
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
(Note 2)
VOL < 1.5V
Tri-State Output
Leakage
IOZL VIN = VDD or GND VDD = 20V
VOUT = 0V
1
2
+25oC
+125oC
-0.4 - µA
-12 - µA
VDD = 18V
3
-55oC
-0.4 - µA
Tri-State Output
Leakage
IOZH VIN = VDD or GND VDD = 20V
VOUT = VDD
1
2
+25oC
+125oC
- 0.4 µA
- 12 µA
VDD = 18V
3
-55oC
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1084


Part Number CD4094BMS
Description CMOS 8-Stage Shift-and-Store Bus Register
Maker Intersil Corporation
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