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CD4089BMS Datasheet

CMOS Binary Rate Multiplier

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CD4089BMS
December 1992
CMOS Binary Rate Multiplier
Features
• High Voltage Type (20V Rating)
• Cascadable in Multiples of 4 Bits
• Set to “15” Input and “15” Detect Output
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
conjunction with an up/down counter and control logic used
to perform arithmetic operations (adds, subtract, divide, raise
to a power), solve algebraic and differential equations,
generate natural logarithms and trigometric functions, A/D
and D/A conversions, and frequency division.
For words of more than 4 bits, CD4089BMS devices may be
cascaded in two different modes: an Add mode and a Multi-
ply mode (see Figures 3 and 4). In the Add mode some of
the gaps left by the more significant unit at the count of 15
are filled in by the less significant units. For example, when
two units are cascaded in the Add mode and programmed to
11 and 13, respectively, the more significant unit will have 11
output pulses for every 16 input pulses and the other unit will
have 13 output pulses for every 256 input pulses for a total of
11 13 189
+=
16 256 256
In the Multiply mode the fraction programmed into the first
rate multiplier is multiplied by the fraction programmed into
the second multiplier. Thus the output rate will be
11 13 143
16 x 16 = 256
• Numerical Control
• Instrumentation
• Digital Filtering
• Frequency Synthesis
Description
CD4089BMS is a low power 4 bit digital rate multiplier that
provides an output pulse rate that is the clock-input-pulse
rate multiplied by 1/16 times the binary input. For example,
when the binary input number is 13, there will be 13 output
pulses for every 16 input pulses. This device may be used in
The CD4089BMS has an internal synchronous 4 bit counter
which, together with one of the four binary input bits, pro-
duces pulse trains as shown in Figure 6.
If more than one binary input bit is high, the resulting pulse
train is a combination of the separate pulse trains as shown
in Figure 6.
The CD4089BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6P
Pinout
CD4089BMS
TOP VIEW
“15” OUT 1
C2
D3
SET TO “15” 4
OUT 5
OUT 6
INHIBIT OUT (CARRY) 7
VSS 8
16 VDD
15 B
14 A
13 CLEAR
12 CASCADE
11 INHIBIT IN (CARRY)
10 STROBE
9 CLOCK
Functional Diagram
CLOCK
INHIBIT
(CARRY) IN
9
11
SET TO
“15”
4
4 BIT
BINARY
COUNTER
CLEAR
13
VDD = 16
VSS = 8
7
BINARY RATE
SELECT INPUTS
A B CD
14 15 2 3
STROBE
10
CASCADE
12
RATE
SELECT
LOGIC
OUT
6
OUT
5
“15” OUT
1
RATE
OUTPUTS
INHIBIT (CARRY) OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1064
File Number 3329


Intersil Electronic Components Datasheet

CD4089BMS Datasheet

CMOS Binary Rate Multiplier

No Preview Available !

Specifications CD4089BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1065


Part Number CD4089BMS
Description CMOS Binary Rate Multiplier
Maker Intersil Corporation
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