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CD4018BMS - CMOS Presettable Divide-By- N Counter

General Description

CD4018BMS types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating.

CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided.

Key Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation 10MHz (typ. ) at VDD - VSS = 10V.
  • Fully Static Operation.
  • 100% Tested for Quiescent Current at 20V.
  • Standardized Symmetrical Output Characteristics.
  • 5V, 10V and 15V Parametric Ratings.
  • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC.
  • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.

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📁 Similar Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4018BMS November 1994 CMOS Presettable Divide-By- “N” Counter Description CD4018BMS types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018BMS units. The counter is advanced one count at the positive clock-signal transition.