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CD4015BMS
December 1992
CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
Pinout
CD4015BMS TOP VIEW
CLOCK B 1 Q4B 2 Q3A 3 Q2A 4 Q1A 5 RESET A 6 DATA A 7 VSS 8 16 VDD 15 DATA B 14 RESET B 13 Q1B 12 Q2B 11 Q3B 10 Q4A 9 CLOCK A
Features
• High-Voltage Type (20V Rating) • Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Input and Output Buffering • 100% Tested For Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and 25oC • Noise Margin (Full Package-Temperature Range) = - 1V at VDD = 5V - 2V at VDD = 10V - 2.