CD4013BMS Datasheet | Intersil

Features - High-Voltage Type (20V Rating) - Set-Reset Capability - Static Flip-Flop Operation - Retains State Indefinitely With Clock Level Either “High” Or “Low” - Medium-Speed Operation - 16 MHz (typ.) Clock Toggle Rate at 10V - Standardized Symmetrical Output Characteristics - 100% Tested for Quiescent Current at 20V - Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100n A at 18V and +25o C - Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V - 5V, 10V and 15V Parametric Ratings - Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Q1 2 CLOCK 1 3 RESET 1 4 D1 5 SET 1 6 VSS 7 Functional Diagram VDD 14 6 5 3 4 8 9 11 F/F2 12 13 F/F1 2 1 SET 1 D1 CLOCK 1 Q1 Q1 Applications RESET 1 - Registers - Counters SET 2 D2 Q2 Q2 - Control Circuits CLOCK 2 Description CD4013BMS consists of two identical, independent data type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive going transition of the clock pulse. Setting or resetting is independent of the clock and is acplished by a high level on the set or reset line, respectively. The CD4013BMS is supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4Q H1B H3W RESET 2 7 VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 7-62 Specifications CD4013BMS Absolute Maximum...