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Intersil Electronic Components Datasheet

CD4011BT Datasheet

CMOS Quad 2-Input NAND Gate

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Data Sheet
CD4011BT
July 1999 File Number 4620.1
CMOS Quad 2-Input NAND Gate
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The CD4011BT, Quad 2-Input NAND gate provides the
system designer with direct implementation of the NAND
function and supplements the existing family of CMOS
gates. All inputs and outputs are buffered.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the CD4011BT are
contained in SMD 5962-96621. A “hot-link” is provided from
our website for downloading.
www.intersil.com/quality/manuals.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9662101TCC
CD4011BDTR
-55 to 125
5962R9662101TXC
CD4011BKTR
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- SEP Effective LET > 75 MEV/gm/cm2
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,
VDD = 10V
• Buffered Inputs and Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
Pinouts
CD4011BT (SBDIP), CDIP2-T14
TOP VIEW
A1
B2
J = AB 3
K = CD 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = GH
10 L = EF
9E
8F
CD4011BT (FLATPACK), CDFP3-F14
TOP VIEW
A
B
J = AB
K = CD
C
D
VSS
1 14
2 13
3 12
4 11
5 10
69
78
VDD
H
G
M = GH
L = EF
E
F
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999


Intersil Electronic Components Datasheet

CD4011BT Datasheet

CMOS Quad 2-Input NAND Gate

No Preview Available !

Schematic and Logic Diagram
CD4011BT
p 14 VDD
1
n
(8, 6, 13)
2
(9, 5, 12)
p
n
VDD
n
p
pp
3 (10, 4, 11)
nn
7 VSS
ALL INPUTS ARE PROTECTED
VSS BY CMOS PROTECTION NETWORK
1(8, 6,13)
2(9, 5, 12)
1 OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
3
(10, 4, 11)
LOGIC DIAGRAM
2


Part Number CD4011BT
Description CMOS Quad 2-Input NAND Gate
Maker Intersil Corporation
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CD4011BT Datasheet PDF






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