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CD40109BMS Datasheet

CMOS Quad Low-to-High Voltage Level Shifter

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CD40109BMS
December 1992
CMOS Quad Low-to-High Voltage Level Shifter
Features
Description
• High Voltage Type (20V Rating)
• Independence of Power Supply Sequence Considerations
- VCC can Exceed VDD
- Input Signals can Exceed Both VCC and VDD
• Up and Down Level Shifting Capability
• Three-State Outputs with Separate Enable Controls
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VCC = 5V, VDD = 10V
- 2V at VCC = 10V, VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD40109BMS contains four low-to-high voltage level shifting
circuits. Each circuit will shift a low voltage digital logic input
signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS
to a higher voltage output signal (E, F, G, H) with logical
1 = VDD and logical 0 = VSS.
The CD40109BMS, unlike other low-to-high level shifting
circuits, does not require the presence of the high voltage
supply (VDD) before the application of either the low voltage
supply (VCC) or the input signals. There are no restrictions
on the sequence of application of VDD, VCC, or the input
signals. In addition, with one exception there are no
restrictions on the relative magnitudes of the supply voltages
or input signals within the device maximum ratings, provided
that the input signal swings between VSS and at least
0.7VCC; VCC may exceed VDD, and input signals may
exceed VCC and VDD. When operated in the mode
VCC > VDD, the CD40109BMS will operate as a high-to-low
level shifter.
The CD40109BMS also features individual three-state out-
put capability. A low level on any of the separately enabled
three-state output controls produces a high impedance state
in the corresponding output.
Applications
• High or Low Level Shifting with Three-State Outputs
for Unidirectional or Bidirectional Bussing
• Isolation of Logic Subsystems Using Separate Power
Supplies from Supply Sequencing, Supply Loss and
Supply Regulation Considerations
The CD40109BMS is supplied in these 16-lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
Pinout
CD40109BMS
TOP VIEW
VCC 1
ENABLE A 2
A3
E4
F5
B6
ENABLE B 7
VSS 8
16 VDD
15 ENABLE D
14 D
13 H
12 NC
11 G
10 C
9 ENABLE C
Functional Diagram
1 OF 4 UNITS
VCC
VDD
LEVEL
A SHIFTER
ENABLE A
LEVEL
SHIFTER
E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-36
File Number 3196


Intersil Electronic Components Datasheet

CD40109BMS Datasheet

CMOS Quad Low-to-High Voltage Level Shifter

No Preview Available !

Specifications CD40109BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
IDD VDD = 20V, VIN = VDD or GND
Input Leakage Current
VDD = 18V, VIN = VDD or GND
IIL VIN = VDD or GND VDD = 20
GROUP A
SUBGROUPS
1
2
3
1
2
TEMPERATURE
+25oC
+125oC
-55oC
+25oC
+125oC
LIMITS
MIN MAX UNITS
- 2 µA
- 200 µA
- 2 µA
-100
-
nA
-1000 -
nA
Input Leakage Current
VDD = 18V
IIH VIN = VDD or GND VDD = 20
Output Voltage
VDD = 18V
VOL15 VDD = 15V, No Load
3
1
2
3
1, 2, 3
-55oC
+25oC
+125oC
-55oC
+25oC, +125oC, -55oC
-100
-
-
-
-
-
100
1000
100
50
nA
nA
nA
nA
mV
Output Voltage
Output Current (Sink)
Output Current (Sink)
VOH15
IOL5
IOL10
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
1, 2, 3
1
1
+25oC, +125oC, -55oC
+25oC
+25oC
14.95
0.53
1.4
-
-
-
V
mA
mA
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
1
+25oC
3.5 - mA
1
+25oC
- -0.53 mA
1
+25oC
- -1.8 mA
1
+25oC
- -1.4 mA
1
+25oC
- -3.5 mA
N Threshold Voltage
P Threshold Voltage
Functional
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
Tri-State Output
Leakage
VNTH
VPTH
F
VIL
VIH
VIL
VIH
IOZL
IOZH
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
VDD = 10V, VOH > 9V, VOL < 1V
VCC = 5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 10V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V, VCC = 10V
VIN = VDD or GND VDD = 20V
VOUT = 0V
VIN = VDD or GND
VOUT = VDD
VDD = 18V
VDD = 20V
VDD = 18V
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
+25oC
-2.8 -0.7
+25oC
0.7 2.8
+25oC
VOH > VOL <
+25oC
VDD/2 VDD/2
+125oC
-55oC
+25oC, +125oC, -55oC -
1.5
V
V
V
V
+25oC, +125oC, -55oC 3.5
-
V
+25oC, +125oC, -55oC -
3V
+25oC, +125oC, -55oC 7 - V
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
-0.4 - µA
-12 - µA
-0.4 - µA
- 0.4 µA
- 12 µA
- 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-37


Part Number CD40109BMS
Description CMOS Quad Low-to-High Voltage Level Shifter
Maker Intersil Corporation
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CD40109BMS Datasheet PDF






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