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Intersil Electronic Components Datasheet

CD40105BMS Datasheet

CMOS FIFO Register

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CD40105BMS
December 1992
CMOS FIFO Register
Features
Description
• 4 Bits x 16 Words
• High Voltage Type (20V Rating)
• Independent Asynchronous Inputs and Outputs
• 3-State Outputs
• Expandable in Either Direction
• Status Indicators on Input and Output
• Reset Capability
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Bit Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto Dialers
• CRT Buffer Memories
• Radar Data Acquisition
CD40105BMS is a low-power first-in-first-out (FIFO) “elastic”
storage register that can store 16 4-bit words. It is capable of
handling input and output data at different shifting rates. This
feature makes it particularly useful as a buffer between asyn-
chronous systems.
Each word position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Loading Data - Data can be entered whenever the DATA-IN
READY (DIR) flag is high, by a low to high transition on the
SHIFT-IN (SI) input. This input must go low momentarily
before the next word is accepted by the FIFO. The DIR flag
will go low momentarily, until that data have been transferred
to the second location. The flag will remain low when all 16-
word locations are filled with valid data, and further pulses
on the SI input will be ignored until DIR goes high.
Continued on next page
Pinout
CD40105BMS
TOP VIEW
3 - STATE
CONTROL
1
DIR 2
16 VDD
15 SO
SI 3
14 DOR
D0 4
13 Q0
D1 5
12 Q1
D2 6
11 Q2
D3 7
10 Q3
VSS 8
9 MR
Functional Diagram
3-STATE
CONTROL
D0
D1
D2
D3
SHIFT IN
SHIFT OUT
4
5
6
7
3
15
1
MASTER
RESET
9
13 Q0
12 Q1
11 Q2
10
Q3
14 DATA-OUT
READY
2 DATA-IN
READY
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1317
File Number 3353


Intersil Electronic Components Datasheet

CD40105BMS Datasheet

CMOS FIFO Register

No Preview Available !

CD40105BMS
Unloading Data - As soon as the first word has rippled to
the output, DATA-OUT READY (DOR) goes high, and data
can be removed by a falling edge on the SO input. This fall-
ing edge causes the DOR signal to go low while the word on
the output is dumped and the next word moves to the output.
As long as valid data are available in the FIFO, the DOR sig-
nal will go high again signifying that the next word is ready at
the output. When the FIFO is empty, DOR will remain low,
and any further commands will be ignored until a “1” marker
ripples down to the last control register, when DOR goes
high. Unloading of data is inhibited while the 3-state control
input is high. The 3-state control signal should not be shifted
from high to low (data outputs turned on) while the SHIFT-
OUT is at logic 0. This level change would cause the first
word to be shifted out (unloaded) immediately and the data
to be lost.
Cascading - The CD40105BMS can be cascaded to form
longer registers simply by connecting the DIR to SO and
DOR to SI. In the cascaded mode, a MASTER RESET pulse
must be applied after the supply voltage is turned on. For
words wider than 4 bits, the DIR and the DOR outputs must
be gated together with AND gates. Their outputs drive the SI
and SO inputs in parallel, if expanding is done in both direc-
tions (see Figures 9 and 11).
3-State Outputs - In order to facilitate data busing, 3-state
outputs are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output.
Master Reset - A high on the MASTER RESET (MR) sets all
the control logic marker bits to “0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be superseded when
the first word is loaded. The shift-in must be low during Mas-
ter Reset.
The CD40105BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Logic Diagram
MASTER
RESET
*9
SHIFT
IN
*3
R
SQ
RQ
1
SQ
2 DATA IN READY
(DIR)
RQ
2
SQ
4 - 15
SHIFT* 15
OUT
*
1 3 - STATE
CONTROL
(OUTPUT
ENABLE)
RQ
16
SQ
DATA
READY
14
(DOR)
R
SQ
*D0 4
*D1 5
*D2 6
*D3 7
CL CL
4
LATCHES
POS 1
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
CL CL
4
LATCHES
VDD
POS 2
CL CL
4
LATCHES
POS 3
VSS
7-1318
CL CL
4
LATCHES
POS 16
3
STATE
OUTPUT
BUFFERS
13 Q0
12 Q1
11 Q2
10 Q3
CL
DETAIL OF LATCHES
p
n
CL
CL
p
n
CL


Part Number CD40105BMS
Description CMOS FIFO Register
Maker Intersil Corporation
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CD40105BMS Datasheet PDF






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