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Intersil Electronic Components Datasheet

CD4007UBMS Datasheet

CMOS Dual Complementary Pair Plus Inverter

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CD4007UBMS
November 1994
CMOS Dual Complementary Pair Plus Inverter
Features
Pinout
• High-Voltage Type (20V Rating)
• Standardized Symmetrical Output Characteristics
• Medium Speed Operation
- tPHL, tPLH = 30 ns (typ) at 10V
• 100% Tested for Maximum Quiescent Current at 20V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
Applications
Q2 (P) DRAIN 1
Q2 (P) SOURCE 2
Q2 GATES 3
Q2 (N) SOURCE 4
Q2 (N) DRAIN 5
Q1 GATES 6
VSS, Q1, Q2, Q3 (N) 7
SUBSTRATES Q1 (N)
SOURCE
CD4007UBMS
TOP VIEW
14 VDD, Q1, Q2, Q3 (P)
SUBSTRATES, Q1(P) DRAIN
13 Q1 (P) SOURCE
12 Q3 (N) DRAIN, Q3 (P) SOURCE
11 Q3 (P) DRAIN
10 Q3 GATES
9 Q3 (N) SOURCE
8 Q1 (N) DRAIN
• Extremely High-Input Impedance Amplifiers
• Shapers
• Inverters
• Threshold Detector
• Linear Amplifiers
• Crystal Oscillators
Description
CD4007BMS types are comprised of three n-channel and
three p-channel enhancement-type MOS transistors. The
transistor elements are accessible through the package ter-
minals to provide a convenient means for constructing the
various typical circuits as shown in Figure 2.
More complex functions are possible using multiple pack-
ages. Numbers shown in parentheses indicate terminals that
are connected together to form the various configurations
listed.
The CD4007BMS is supplied in these 14 lead outline pack-
ages:
Functional Diagram
14 2
pp
11
p
6 133
1 10
12
85
nn
n
74
9
TERMINAL NO. 14 - VDD
TERMINAL NO. 7 - VSS
Braze Seal DIP H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-666
File Number 3291


Intersil Electronic Components Datasheet

CD4007UBMS Datasheet

CMOS Dual Complementary Pair Plus Inverter

No Preview Available !

Specifications CD4007UBMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 0.5 µA
2
+125oC
- 50 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 0.5 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.0 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 4.0
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
2.5 V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 12.5
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs
7-667


Part Number CD4007UBMS
Description CMOS Dual Complementary Pair Plus Inverter
Maker Intersil Corporation
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