CD4001BMS Datasheet | Intersil

CD4000BMS, CD4001BMS CD4002BMS, CD4025BMS November 1994 CMOS NOR Gate Pinouts CD4000BMS TOP VIEW NC 1 NC 2 A 3 B 4 C 5 H=A+B+C 6 VSS 7 14 VDD 13 F 12 E 11 D 10 K = D + E + F 9 L=G 8 G NC = NO CONNECTION Features - High-Voltage Types (20V Rating) - Propagation Delay Time = 60ns (typ.) at CL = 50p F, VDD = 10V - Buffered Inputs and Outputs - Standard Symmetrical Output Characteristics - 100% Tested for Maximum Quiescent Current at 20V - 5V, 10V and 15V Parametric Ratings - Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100n A at 18V and +25o C - Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V - Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s CD4001BMS TOP VIEW A 1 B 2 J=A+B 3 K=C+D 4 C 5 D 6 VSS 7 14 VDD 13 H 12 G 11 M = G + H 10 L = E + F 9 F 8 E NC = NO CONNECTION Description CD4000BMS CD4001BMS CD4002BMS CD4025BMS - Dual 3 Plus Inverter - Quad 2 Input - Dual 4 Input - Triple 3 Input CD4002BMS TOP VIEW J=A+B+C+D 1 A 2 B 3 C 4 D 5 NC 6 VSS 7 14 VDD 13 K = E + F + G + H 12 H 11 G 10 F 9 E 8 NC NC = NO CONNECTION CD4000BMS, CD4001BMS, CD4002BMS, and CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4000BMS, CD4001BMS, CD4002BMS and the CD4025BMS is supplied in these 14 lead outline...