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Intersil Electronic Components Datasheet

CD22402 Datasheet

Sync Generator for TV Applications and Video Processing Systems

No Preview Available !

May 1999
Semiconductor
CD22402NO
Call
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[ /Title
(CD2240
2)
/Subject
(Sync
Genera-
tor for
TV
Applica-
tions and
Video
Process-
Features
• Interlaced Composite Sync Output
• Automatic Genlock Capability
• Crystal Oscillator Operation
• 525 or 625 Line Operation
• Vertical Reset Option
• Wide Power Supply Operating Voltage . . . . . 4V to 15V
Applications
• Cameras
• Monitors and Displays
• CATV
• Teletext
• Video Games
• Sync Restorer
• Video Service Instruments
Part Number Information
PART NUMBER
CD22402D
CD22402E
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 24 Ld SBDIP
-40 to 85 24 Ld PDIP
PKG.
NO.
D24.6
E24.6
Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that
produces all the timing signals required to drive a fully 2-to-1
interlaced 525-line 30-frame/second, or 625-line 25-frame/sec-
ond TV camera or video processing system. A complete sync
waveform is produced which begins each field with six serrated
vertical sync pulses, preceded and followed by six half-width
double frequency equalizing pulses. The sync output is gated by
the master clock to preserve horizontal phase continuity during
the vertical interval.
The CD22402 can be operated either in “genlock” mode, in
which it is synchronized with a reference sync pulse train from
another TV camera, or in “stand-alone” mode, in which it is syn-
chronized with a local on-chip crystal oscillator (the crystal and
two passive components are off chip). Also, the circuit can
sense the presence or absence of a reference sync pulse train
and automatically select the “genlock” or “stand-alone” mode.
A frame sync pulse is produced at the beginning of every odd
field. The vertical counter can be reset to either the first equalizing
pulse or the first vertical sync pulse of the vertical interval. The
interlaced sync provided by the CD22402 differs from RS-170 by
having slightly narrower sync and equalizing pulses. The clock
frequency of 32 times horizontal rate allows for approximately 4µs
horizontal pulse widths and 2µs equalizing pulses. Otherwise
operation can be phase locked to a color sub-carrier for a full
interlaced operating system.
The CD22402 is operable with a single supply over a voltage
range of 4V to 15V.
Pinout
CD22402 (PDIP, SBDIP)
TOP VIEW
DELAY, GENLOCK TO CRYSTAL OSCILLATOR 1
CRYSTAL OSCILLATOR FEEDBACK TAP 2
VSS 3
HORIZONTAL DRIVE OUTPUT 4
MIXED SYNC OUTPUT 5
GENLOCK OSCILLATOR CAPACITOR CONNECTION 6
MIXED BEAM BLANKING OUTPUT 7
VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE 8
VERTICAL DRIVE OUTPUT 9
VERTICAL RESET TO FIRST VERTICAL SYNC PULSE 10
HORIZONTAL CLAMP OUTPUT 11
VSS 12
24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR
23 MASTER FREQUENCY INPUT
22 R-C CONNECTION FOR GENLOCK OSCILLATOR
21 DELAY, GENLOCK TO CRYSTAL OSCILLATOR
20 GENLOCK INPUT (COMPOSITE SYNC)
19 VDD
18 525 LINE TO 625 LINE OPERATION SWITCH
17 VERTICAL PROCESSING BLANKING OUTPUT
16 SHORT VERTICAL DRIVE OUTPUT
15 FRAME SYNC OUTPUT (ODD FIELD)
14 HORIZONTAL PROCESSING BLANKING OUTPUT
13 MIXED PROCESSING BLANKING OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
8-40
File Number 1686.5


Intersil Electronic Components Datasheet

CD22402 Datasheet

Sync Generator for TV Applications and Video Processing Systems

No Preview Available !

CD22402
Pin Descriptions
PIN NO. SYMBOL
DESCRIPTION
1 XRC Delay, Genlock to Crystal Oscillator. Resistor, diode and capacitor connection for delay that automatically
turns on the crystal oscillator when the genlock input is removed. When the signal on Terminal 1 is high the crys-
tal oscillator is inhibited. Typical values for R and C are 1Mand 0.001µF. For operation as a crystal controlled
stand alone sync generator without genlock, Terminal 1 should be hardwired to VSS.
2 XTP Crystal Oscillator Feedback Tap. Feedback connection (tap) for crystal oscillator. When a crystal (shunted by
a 1Mresistor) is connected between this terminal and Terminal 23, and a 100pF capacitor is connected from
this terminal to VSS, the sync generator creates its own master frequency. For a 525-line, 30-frame/second ras-
ter, the crystal frequency is 504.000kHz (Note 1); and for a 625-line, 25-frame/second raster, the crystal frequen-
cy is 500.000kHz (Note 1).
3 VSS Negative Power Supply Voltage. This terminal must be hardwired to Terminal 12 (VSS).
4 HD Horizontal Drive Output
5 MS Mixed Sync Output
6 C Capacitor Connection for R-C Genlock Oscillator
7 MBB Mixed Beam Blanking Output
8 VRE Vertical Counter Reset to First Equalizing Pulse. A low level signal on this terminal resets the vertical counter
to the first equalizing pulse of a field. When not in use this terminal should be connected to VDD.
9 VD Vertical Drive Output
10 VRV Vertical Counter Reset to First Vertical Sync Pulse. A low level signal on this terminal resets the sync gen-
erator to the first vertical sync pulse of a field. For genlock operation, Terminal 10 is used as a resistor and ca-
pacitor connection for an integrator network that detects vertical sync pulses in a master sync waveform to which
the sync generator is to be genlocked. R is 22k, and C is 0.001µF. When not in use this terminal should be
connected to VDD.
11 HC Horizontal Clamp Output
12 VSS Negative Power Supply Voltage
13 MPB Mixed Processing Blanking Output
14 HPB Horizontal Processing Blanking Output
15 FS2 Frame Sync Output (Odd Field). A pulse coinciding with the first equalizing pulse is produced at the beginning
of every odd field.
16 SVD Short Vertical Drive Output
17 VPB Vertical Processing Blanking Output
18 SW Operation Switch for 525-Line or 625-Line Raster. A high level signal on Terminal 18 causes the sync gener-
ator to generate a 625-line raster. An internal pulldown resistor is connected to Terminal 18, so in the absence
of an applied input to this terminal, a 525-line raster is produced.
19 VDD Positive Power Supply Voltage. VDD can be any voltage between +4 and +15 relative to VSS.
20 GEN Genlock Input Composite Sync. A negative going reference mixed sync waveform applied to Terminal 20 dis-
ables the crystal oscillator and locks the R-C genlock oscillator to the horizontal pulses of the reference sync
waveform. Vertical sync detection is achieved by an R-C integrator connected from Terminal 20 to Terminal 10
(vertical reset to first vertical sync pulse). An internal pull-up resistor is connected to Terminal 20 so that in the
absence of an applied input the crystal oscillator is enabled and the R-C genlock oscillator is disabled.
21 XR Delay, Genlock to Crystal Oscillator, Resistor and Diode Connection for Delay, Genlock to Crystal Oscil-
lator. Automatically turns on the crystal oscillator when the input to Terminal 20 is removed.
22 RC Resistor and Capacitor Connection for Genlock Oscillator. If the genlock oscillator is not used this terminal
should be connected to VSS. C should be 100pF, and R should be a 10kpotentiometer.
23 XIN Master Frequency Input.
24 R Resistor Connection for Genlock Oscillator.
NOTE: 32 times horizontal frequency.
8-41


Part Number CD22402
Description Sync Generator for TV Applications and Video Processing Systems
Maker Intersil Corporation
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CD22402 Datasheet PDF






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