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IRF6711STRPBF - Power MOSFET

Download the IRF6711STRPBF datasheet PDF. This datasheet also covers the IRF6711SPBF variant, as both devices belong to the same power mosfet family and are provided as variant models within a single manufacturer datasheet.

Description

The IRF6711STRPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve improved performance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile.

Features

  • ward Voltage 90 80 70 ID, Drain Current (A) Fig11. Maximum Safe Operating Area Typical VGS(th) Gate threshold Voltage (V) 3.0 2.5 60 50 40 30 20 10 0 25 50 75 100 125 150 T C , Case Temperature (°C) 2.0 ID = 25µA ID = 250µA ID = 1.0mA ID = 1.0A 1.5 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( °C ) Fig 12. Maximum Drain Current vs. Case Temperature 300 EAS , Single Pulse Avalanche Energy (mJ) Fig 13. Typical Threshold Voltage vs. Junction Temperature ID TOP 0.91A 1.16A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IRF6711SPBF-InternationalRectifier.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by International Rectifier (now Infineon)

Part Number Description
IRF6711SPBF Power MOSFET
IRF6710S2 Power MOSFET
IRF6710S2TR1PbF Power MOSFET
IRF6710S2TRPbF Power MOSFET
IRF6712SPBF N-Channel HEXFET Power MOSFET

Full PDF Text Transcription

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PD - 96280 IRF6711SPbF IRF6711STRPbF l l l l l l l l l RoHS Compliant and Halogen Free  Low Profile (<0.7 mm) Dual Sided Cooling Compatible  Ultra Low Package Inductance Optimized for High Frequency Switching  Ideal for CPU Core DC-DC Converters Optimized for Control FET Application Compatible with existing Surface Mount Techniques  100% Rg tested Typical values (unless otherwise specified) DirectFET™ Power MOSFET ‚ RDS(on) Qgs2 1.8nC VDSS Qg tot VGS Qgd 4.4nC RDS(on) Qoss 9.5nC 25V max ±20V max 3.0mΩ @ 10V 5.2mΩ @ 4.5V Qrr 21nC Vgs(th) 1.8V 13nC SQ Applicable DirectFET Outline and Substrate Outline (see p.
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