PF48F3000P0ZTQ0 Datasheet | Intel Corporation

Features - High performance - Security - 85/88 ns initial access - One-Time Programmable Registers: - 40 MHz with zero wait states, 20 ns clock-todata output synchronous-burst read mode - 64 unique factory device identifier bits - 64 user-programmable OTP bits - 25 ns asynchronous-page read mode - Additional 2048 user-programmable OTP bits - 4-, 8-, 16-, and continuous-word burst mode - Selectable OTP Space in Main Array: - Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ) - 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration) - 1.8 V buffered programming at 7 µs/byte (Typ) - Absolute write protection: VPP = VSS - Architecture - Multi-Level Cell Technology: Highest Density at Lowest Cost - Power-transition erase/program lockout - Individual zero-latency block locking - Individual block lock-down - Asymmetrically-blocked architecture - Software - Four 32-KByte parameter blocks: top or - 20 µs (Typ) program suspend bottom configuration - 20 µs (Typ) erase suspend - 128-KByte main blocks - Intel® Flash Data Integrator optimized - Voltage and Power - VCC (core) voltage: 1.7 V - 2.0 V - VCCQ (I/O) voltage: 1.7 V - 3.6 V - Standby current: 55 µA (Typ) for 256-Mbit - Basic mand Set and Extended mand Set patible - mon Flash Interface capable - Density and Packaging - 4-Word synchronous read current: 13 m A (Typ) at 40 MHz - 64/128/256-Mbit densities in 56-Lead TSOP package - Quality and...