83C196LC Datasheet | Intel Corporation

feature an enhanced synchronous serial I/O (SSIO) port for more flexible munication to other devices. The enhanced SSIO is patible with Motorola’s Serial Peripheral Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was removed for use in those applications that use an off-chip A/D converter. The MCS® 96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs. The 83C196LC, 83C196LD are posed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 patible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and pare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming language. COPYRIGHT © INTEL CORPORATION, 1996 December 1996 Order Number: 272805-001 83C196LC, 83C196LD - AUTOMOTIVE Port 6 Port 0 Watchdog...