128P308
Features
- High performance
..
- Security
- 85/88 ns initial access
- One-Time Programmable Registers:
- 64 unique factory device identifier bits
- 40 MHz with zero wait states, 20 ns clock-to- 64 user-programmable OTP bits data output synchronous-burst read mode
- Additional 2048 user-programmable OTP bits
- 25 ns asynchronous-page read mode
- Selectable OTP Space in Main Array:
- 4-, 8-, 16-, and continuous-word burst mode
- 4x32KB parameter blocks + 3x128KB main
- Buffered Enhanced Factory Programming blocks (top or bottom configuration) (BEFP) at 5 µs/byte (Typ)
- Absolute write protection: VPP = VSS
- 1.8 V buffered programming at 7 µs/byte (Typ)
- Power-transition erase/program lockout
- Architecture
- Individual zero-latency block locking
- Multi-Level Cell Technology: Highest Density
- Individual block lock-down at Lowest Cost
- Software
- Asymmetrically-blocked architecture
- 20 µs (Typ) program suspend
- Four 32-KByte parameter blocks: top or
- 20 µs (Typ) erase suspend...
